Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu, Reliability and Failure analysis, techniques and methods
Abstract: This paper reports the effect of composition deviation of CuAl2 on electromigration (EM) property. EM property was measured in the temperature range of 225-325 °C at a current density of 1 MA/cm2. At 275 °C, the void formation rate of Al-rich sample was found to be 1.1-1.2 times faster than that of stoichiometric samples, while it was reduced to 1/5 for Cu-rich samples. The activation energy of Al-rich and stoichiometric samples is found to be 1.16 eV, while that of Cu-rich sample is 1.59 eV. These results show that shifting the composition to Cu-rich side enhances the electromigration properties and the composition has been found to have a significant effect on electromigration of intermetallic compounds.

Keywords: Reliability and Failure analysis, techniques and methods
Abstract: Physics-based numerical simulations have been widely employed for understanding electromigration (EM) induced voiding in Cu interconnects. Yet, their application has remained limited to exploratory studies given their computational cost. To achieve fast, yet accurate, void dynamics simulations, in this study, a neural network (NN) is trained to determine local current density distributions around void surfaces. Up to 85% reduction of computational time was achieved by replacing the finite- element (FE) solver with the NN. The model was used to investigate the impact of interconnect linewidth, line and via aspect ratio and microstructure on void dynamics.

Keywords: Reliability and Failure analysis, techniques and methods, Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: We evaluated the reliability of Semi-Damascene interconnects system fabricated by direct metal etch of Ru and Air-Gap as inter-metal dielectric. We show that intrinsically Ru does not drift into SiN and SiCO. Line-line TDDB results with Air-Gap widths of 8-16 nm (fixed line width of 10 nm) show a higher field acceleration factor compared to Dual-Damascene Ru/low-k systems and pass 10 years lifetime with Vmax > 0.75 V at 100oC for industry relevant line lengths. To address concerns related to moisture intake in Air-Gaps, we carried out humidity tests which showed no significant change in capacitance, leakage and VBD after 1000h at 85C/85%RH. We also present that fully self-aligned vias pass electromigration and thermal storage tests.

Keywords: Reliability and Failure analysis, techniques and methods, Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: We show that filling vias with refractory metals deposited barrierless (like W or Ru) eliminate the reliability concerns raised in previous studies on Co via prefill. In particular, we characterized the reliability of W-Cu hybrid systems landing on Ru and Co and compare them with earlier results using Co and Ru via prefill. Via electromigration results show expected parameters for systems with SiCN cap and failure analysis after via electromigration shows no voiding in the W vias. Long term thermal storage experiments for 1200 h indicate that W vias are reliable and do not suffer from voiding or metal intermixing.

Keywords: Reliability and Failure analysis, techniques and methods, Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: The need of surface-localized thermal processing is strongly increasing especially w.r.t three-dimensionally (3D) integrated electrical devices. UV laser annealing (UV-LA) technology well addresses this challenge. Particularly UV-LA can reduce resistivity by enlarging metallic grains in lines or thin films, irradiating only the interconnects for short timescales. However, the risk of failure in electrical performance must be correctly managed, and that of UV-LA has not been deeply studied yet. In this work microsecond-scale UV-LA is applied on a stack comparable to an interconnect structure (dielectric/Cu/Ta/SiO2/Si) in either melt or sub-melt regime for grain growth. The failure modes such as (i) Cu diffusion into SiO2, (ii) O incorporation into Cu, and (iii) intermixing between Cu and Ta are investigated.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: Research on graphene processes for the applications to interconnects and electrodes, such as graphene caps, direct deposition of multi-layer graphene, and stable intercalation doping, is steadily progressing. Furthermore, attention will be paid to the application of graphene, which has a high kinetic inductance, to RF devices. Here, I will give an overview of recent research topics toward the practical application of graphene and discuss the issues.

Keywords: Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning
Abstract: This invited talk describes the advanced process technologies for continuous logic transistor and interconnect evolution towards 2nm node and beyond. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu extension, Post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.

Keywords: Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning, Process integration, via/trench patterning, Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: ULK glasses exhibit significant changes in both their structure and properties under nanoscale confinement which they are exposed to in microelectronic applications where ULK glasses such as hybrid organic-inorganic organosilicates (OSG) are deposited into nano-scale patterns in silicon wafers to perform as electrical insulators. It is crucial to elucidate the role of nanoscale device effects on different OSG materials and explore design strategies to limit extra degradation in their mechanical reliability. Accordingly, we present computational results showing that hyperconnected hybrid OSG precursors with cyclic organic rings assemble relatively more homogenously under confinement which leads to the formation of smaller nanovoids with superior mechanical reliability compared to more commonly used ethylene bridged OSG hybrids.

Keywords: Process integration, via/trench patterning, Reliability and Failure analysis, techniques and methods, Memory architecture: CBRAM, PCRAM, ReRAM, MRAM, DRAM, 3DNAND
Abstract: Cu interconnect structure is investigated to improve TDDB property of Cu line-to-line with scaled pitch in high voltage circuit for 3D flash memory. Recessed Cu and barrier-metal structure reduce unexpected local electric field concentration, and suppress Cu2+ or other cations drift into intra metal dielectrics. Those result in better reliability characteristics regarding TDDB life time than that of conventional structure.

Keywords: Process integration, via/trench patterning, Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu, Reliability and Failure analysis, techniques and methods
Abstract: High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 15.5 nm and AR = 7.7 are successfully integrated in a 3nm node chip. 3-level SV directly connects Mx with Mx+3 metal layers, without connecting to the intermediate two metal layers. Enabling such high AR SV is achieved by fine tuning the SV etch process to guarantee uniform SV landing and a straight vertical profile. Electrical results show that 3-level Kelvin SVs provide an average resistance of 58 Ω, yielding > 95 % for the best conditions, improving our previously reported yield values of 2-level with enhanced AR [1]. 3-level SVs gave a resistance 13% lower than the conventional 2-level stacked via configuration [2]. Metallization stack used was 0.3 nm of ALD TiOx as an adhesion layer, followed by a Ru CVD deposition of 70 nm. Thermal shock tests of 500 hours, between 50 ℃ and 125 ℃, performed on intervals of 15 min each, showed that the Kelvin resistance values remained virtually unchanged. Therefore, 3-level SV are stable after thermal shock tests, proving that they are a robust scaling booster for the 3nm node.

Keywords: Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning, Process integration, via/trench patterning, Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: This paper describes strong galvanic corrosion effect of Co liner on atomic layer deposition (ALD) TaN barrier during Cu CMP. Compared to Co liner on physical vapor deposition (PVD) TaN, Co liner on ALD TaN was more easily corroded resulting in Cu void defects. We investigated characteristic differences between ALD and PVD TaN, and identified the root cause of Cu void formation is higher nitrogen content in ALD TaN film. We could minimize the galvanic corrosion and the resulting Cu voids by reinforcing plasma treatments after ALD TaN deposition.

Keywords: Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: The device nodes of 2nm and beyond face great challenges on performance, power, area and cost since the patterning needs more EUV layers and the resistance of contacts and wires increase as the interconnect scales down. Industries are struggling to extend Cu interconnect by reducing barrier metal thickness and implementing selective barrier metal, however, the resistance is already higher than the values required to meet the device performance target. Alternative metals can be the solution of these challenges due to its low resistivity at the line width smaller than around 10 nm. Also, it gives chances to grow the single grain at the hole type patterns and deposit metals selectively from the via bottoms. Furthermore, direct metal etch scheme can be considered with alternative metals, which provides the lower resistance than damascene at same aspect ratio and the easy way to make airgap between patterned wires. Direct etch schemes with airgap can be the only solution to achieve the low resistance and the low capacitance at the same time. Another disruptive solution is to adopt new schemes such as backside power delivery network and buried power rail, which enable more wide wires for delivering power on the backside of the wafer and give more spaces to route in the interconnect layers at the front side of the wafer. However, it entails difficult techniques of wafer bonding, thinning, and making nano-sized TSV. Also we have to choose proper metallization to fill the TSV to have low resistance with less defects.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: This study illustrates that the mechanism of line wiggling (repetitive line CD variability) caused by post-Cu alternative metals deposition can be characterized by a “zipping up” behavior of alternative metals, which is related to their surface energy. The repetitive line CD variability caused a line resistance increase, which resulted in overall circuit performance degradation. It has been observed that the extent of line wiggling has strong dependencies on several parameters such as A/R (Aspect Ratio) of trenches and the modulus of IMD (Inter Metal Dielectric). We have demonstrated Ru interconnects without line wiggling by using a sacrificial TiN template which is replaced with low-k material after line fabrication.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu, Process integration, via/trench patterning
Abstract: This work reports for the first time, a middle-of-line (MOL) compatible, barrier/liner-less ALD molybdenum (Mo) process on SiO2 used for Via-to-buried-power-rail (VBPR) and contact-to-active (M0A) dual-damascene metallization. We also compare the MOL-compatible ALD process with the front-end-of-line (FEOL)-compatible ALD process used for BPR fill as reported in [1]. In addition, we report that Mo-BPR can withstand 800 °C anneal, demonstrating its compatibility with high thermal budgets of FEOL. Furthermore, we demonstrate for the first time, integrated (i.e. w/o air-break) precleans prior to Mo-VBPR deposition for contact formation with Mo-BPR. The precleans remove MoOx from Mo-BPR surface proven by SIMS characterization at blanket film level. The effectiveness of precleans is further proven at via level with a good agreement between measured and predicted Mo-VBPR resistance (R) landing on Mo-BPR. Finally, the first downstream electromigration tests on Mo-BPR annealed at 800 °C, show no failures for >150 h at 5 MA/cm2 & 330 °C proving its robust behavior.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu, Process integration, via/trench patterning
Abstract: Ru semi-damascene has been recently considered as a promising candidate to replace the conventional Cu dual damascene to meet the continued RC scaling needs in sub-2nm technology nodes. In this work, Ru lines with critical dimension of 9-10 nm and AR 3-6 targeting MP18-MP26 were fabricated in IMEC 300-mm pilot line using EUV-SADP technique and subsequent direct etch of Ru films for the first time. We demonstrate the optimizations made in patterning, metal etch, and clean that enabled the successful fabrication of Ru lines. Single line resistance of 10µm Ru with AR 3 shows that >90% of the devices meet the resistance target of <700 Ω/μm for MP20-26 and ~50% for MP18. Leakage current measurements between the core-defined and gap-defined Ru lines show >90% of devices meet the leakage target of 10-11A/um.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: This paper presents a technology-circuit co-optimization flow to achieve the best balance between wire resistance and capacitance in advanced technology nodes. It is shown that increasing the wire width to spacing ratio improves the circuit performance by up to 17.73%. In addition, we perform a sensitivity analysis on the resistance of interconnects within standard cells at the 7nm node where we show that a 2X hypothetical increase results in a 5.02% degradation in overall circuit performance, whereas a 0.5X hypothetical resistance improvement results in a 2.11% decrease in power.

Keywords: Reliability and Failure analysis, techniques and methods, Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: We present a methodology for predicting line-to-line reliability of Air-Gap schemes, which accounts for line edge roughness and electric field enhancement. Our model is calibrated to the intrinsic reliability properties of the Air-Gap interface dielectrics, which are characterized by performing time-dependent dielectric breakdown measurements on planar capacitors. We validate our model to experimental TDDB data from Ru/Air-Gap semi-damascene interconnects and predict that deeper Air-Gaps, extending into the bottom interlayer dielectric, can significantly boost the reliability of Air-Gaps schemes.

Keywords: Reliability and Failure analysis, techniques and methods, Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: In this work, the microstructural and stress evolution of Mo and Ru films is studied at relevant temperatures for interconnect processing. Wafer bow measurements, transmission electron microscopy (TEM), in-situ XRD (IS-XRD), and microelectromechanical systems (MEMS) were used to determine stress and thermal stress evolution for 10 to 30 nm thick films. We show that Mo and Ru present a complex evolution of the stress evolution during thermal cycling that can be linked to the creation and diffusion of point defects.

Keywords: Advanced material/process characterization, design-technology co-optimization, and modelling techniques
Abstract: We investigate NiAl as a potential alternative for Cu in future interconnect metallization schemes. NiAl was deposited by physical vapor deposition at temperatures up to 420ºC. A resistivity of 30 µΩcm was achieved for a 7 nm thick NiAl film at a deposition temperature of 420ºC with in-situ Si capping at 100ºC. A resistivity of 18 µΩcm was reached for 22 nm thick NiAl in identical conditions. Depositing epitaxial NiAl on Ge (100) led to an even lower resistivity of 14.3 µΩcm for a 22 nm film since better crystallinity was obtained. Challenges and integration feasibility are discussed.

Keywords—Aluminides; alternative metals; thin films; resistivity; interconnect

Keywords: Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning
Abstract: Titanium nitride (TiN) thin films are utilized as diffusion barriers for Co and W metal layers as well as the gate metal barrier in CMOS and memory devices due to the material’s low resistivity; TiN is also used as a coating for hard disk drives[1]. Low resistivity TiN in commercial devices has been deposited by plasma-enhanced ALD (PE-ALD) and by physical vapor deposition. However, for high aspect ratio features and horizontal vias, deposition by thermal ALD is needed to enhance the conformality of the deposition process. In the present work, it is shown that the resistivity can be decreased below 220 uΩ-cm with a non-halogenated precursor at 425 oC by using a Ti precursor with high thermal stability and by reducing the oxygen and carbon contents in the films using a highly reactive co-reactant, anhydrous hydrazine (N2H4).

Titanium tetrachloride (TiCl4), as well as three metal-organic precursors and anhydrous hydrazine (N2H4, Rasirc, Brute Hydrazine), were employed with ultra-high purity nitrogen purge gas. Films formed with the three halogen-free precursors, TDMAT (tetrakis(dimethylamino)titanium), TDEAT (tetrakis(diethylamino)titanium), and TEMATi (tetrakis(ethylmethylamido)titanium) were compared to TiCl4 for resistivity and conformality. The TiN ALD chamber was connected to an in-situ Auger electron spectrometer (RBD Instruments), which determined the atomic composition of ALD TiN. Pulse lengths and purge times were optimized on HF-cleaned Si (100) or degreased SiO2. For TiCl4, the optimized deposition temperature was 425 oC and the optimal pulse times were 300 ms for TiCl4 and 3600 ms for N2H4, but for the metal-organic precursors, different optimized pulsed lengths and deposition temperatures were needed. Four-point probe (Ossila) measurements were performed to determine the resistivity of TiN thin films on degreased SiO2 substrates. Nanoscale patterned samples with horizontal vias (aspect ratio: 1:5) were used to verify the conformality of the low resistivity TiN thin films. TEM was employed to analyze the conformality of TiN thin films.

Keywords: Process integration, via/trench patterning, Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: To overcome the micro loading effect that happens during M2 trench etch, an Al2O3 etch stop layer is successfully implemented in our test vehicle with minimum 21nm metal pitch dual-damascene interconnects. Two integration challenges are investigated: via opening difficulty with 2nm Al2O3 layer and undercut issue with 5nm Al2O3 layer. Potential solutions are proposed accordingly. Post Ru metallization, good morphological and electrical results are demonstrated for the split with 5nm Al2O3.

Keywords: 3D integration & packaging concerns: WtW/CtW bonding, Interposer, Through Si Via, CPI, Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning
Abstract: Spin transfer torque magnetic random-access memory (STT-MRAM) with magnetic tunnel junction (MTJ) devices, which are among the spintronics devices, have many advantages, such as high programing speed and sufficient endurance. Therefore, currently, the spintronics devices are being thoroughly studied. However, they suffer from low thermal stability; thus, low-temperature integration and packaging technologies need to be developed. In this study, we applied In/Au microbumps, which have low bonding temperature and high thermal stability, to a flip-chip bonded STT-MRAM onto a Si interposer. No effect of the flip-chip bonding process on the STT-MRAM cell was observed. Investigation results indicated that low-temperature bonding technology with In/Au microbumps are promising for accelerating the integration of spintronics devices.

Keywords: Novel System and Emerging Technology: Energy harvesting, brain-inspired computing, Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning
Abstract: Current application was found to enhance the crystallinity of multilayer graphene during CVD using a Ni catalyst layer. However, the reduction of surface roughness has been the issue. The effect of current to the Ni catalyst layer was investigated, and it was found that the current promotes the growth of Ni (111) grains, leading to the enhanced compressive stress. After reaching the stress limit, the Ni microstructure changed again and the stress was relaxed. Such microstructure changes in the Ni film correlated with the surface roughness.

Keywords: Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning, 3D integration & packaging concerns: WtW/CtW bonding, Interposer, Through Si Via, CPI
Abstract: Chemical mechanical polishing (CMP) process have been heavily utilized in throughout the semiconductor manufacturing processes from front-end to back-end for decades. However, CMP process is still in its early stage for advanced packaging because of the difficulties observed with implementation of CMP process such as: low removal rate, poor selectivity, and elevated surface roughness and defects on the organic polymer film. Nevertheless, CMP process is becoming an essential part of the 2D advanced packaging and beyond in order to achieve smaller pitch and improve re-distribution layer (RDL) process. In this paper, we focus on highly tunable removal rate and selectivity, and low defectivity performance slurry for epoxy mold compound (EMC) with silica filler and Cu pads.

Keywords: Contacts on MOS devices: Silicide, III-V, 2D materials
Abstract: The purpose of this work is to obtain the low specific contact resistivity on n-GaN. We investigated the Schottky barrier height between various metals and GaN and found that Fermi level pinning occurred at the interface between metals and GaN. We also attempted to reduce the specific contact resistivity using MIS structure in order to release Fermi level pinning. We selected GaOx and TiOx for the insulator materials and obtained the low specific contact resistivity of 7.1×10-7 Ω·cm2 with GaOx on n-GaN having Si doping concentration of 2x1018 cm-3.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: Electrospinning technology was introduced to the formation of air-gap in metal interconnection. A polyimide fiber-cluster layer was made with this technology on the line and space (L/S) patterns. After the hot melting of the layer, a perfect air-gap structure was created. It is different from the non-conformal CVD, and the sacrificial layer method. A polyimide nano-fiber-cluster layer (PI-nFCL) formed by E/S is changed into a dense polyimide (PI) film. Then it looks like a bridge on the patterns showing a perfect air-gap-like space.

Keywords: 3D integration & packaging concerns: WtW/CtW bonding, Interposer, Through Si Via, CPI, Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning
Abstract: Through silicon via (TSV) with a high aspect ratio is in great demand in three-dimension (3D) integration technology. This work demonstrates a wet process flow for high aspect ratio TSV metallization using electroless cobalt deposition and copper electroplating. The electroless deposited Co liner and alkaline electroplating deposited Cu seed layer are successfully integrated into a 4 μm×50 μm TSV with an aspect ratio higher than 10:1. The electroless Co liner layer with a step coverage of up to 97% is formed on the TiN barrier by adding a suppressor additive in the plating bath. Then, a conformal alkaline Cu seed layer with step coverage of 75% is deposited on the Co liner layer throughout the TSV. Finally, the TSV is filled by the acidic Cu electroplating without voids, indicating the high quality of the Co liner layer as well as the Cu seed layer and the feasibility of the demonstrated wet process flow in the high aspect ratio TSV.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu, Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning
Abstract: Ru deposition is required for advanced technology nodes (< 32 nm) because it can improve the performance with low resistivity in nanoscale features. This study reports electrochemical reactions of Ru and behaviors of additives on Ru electrodeposition using cyclic voltammetry (CV) and linear sweep voltammetry (LSV). Ru3+ forms complexes, and the complexes are reduced on the Ru surface. It was confirmed that disodium 3,3'-Dithiobis(1-propanesulfonate) (SPS) could accelerate Ru deposition, and polyvinylpyrrolidone (PVP) could suppress Ru deposition. Also, NaBr showed suppression, and it can form a strong suppression layer with PVP. Focused ion beam (FIB) image shows the filling of Ru with those additives.

Keywords: Reliability and Failure analysis, techniques and methods, Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: Electromigration induced degradation of gold metallization used for GaAs devices is a significant, but not sufficiently investigated phenomenon. In this work, a complete physics-based analysis of electromigration in gold is presented. In particular, the dependence of statistical failure features on the variation of geometric properties is investigated. The experimentally observed impact of the interconnect geometry on the mean failure time and the associated standard deviation of the failure times is well reproduced by numerical simulations.

Keywords: Materials and Unit Processes: Dielectrics, Metals, barriers, Wet, CMP, PVD, CVD, patterning, Reliability and Failure analysis, techniques and methods
Abstract: Two-dimensional (2D) materials have been suggested to offer a viable route towards further miniaturization of interconnect technology as new diffusion barriers (DBs), replacing current industry standards at low thickness regime. We investigate new copper DBs to be used in back end of line (BEOL) interconnect structures, based on 2D materials grown on a large scale. The films are characterized using transmission electron microscopy, X-ray photoelectron spectroscopy and Raman spectroscopy to verify their structural quality and chemical composition. An experimental protocol is presented to assess the performance of these films as DBs, including a device fabrication scheme and a measurement scheme that both allow for the comparison of different barriers. This study establishes the difference in barrier properties as a function of film thickness based on their different crystal structure, comparing 2D materials with industry standard TaN barriers, thus evaluating the potential of 2D materials for future, scaled down, interconnect technology. This screening protocol also enables optimization of the growth conditions for improved DBs.

Keywords: Advanced interconnect metallizations with low-k dielectrics as well as optical, wireless, and carbon-based interconnects, beyond Cu
Abstract: Regarding the resistance reduction in the fine metal line of the semiconductor device, the annealing effect by the excimer laser has been confirmed. KrF excimer laser irradiated to Cu and Ru as fine metal line materials, and the change in resistivity and the surface condition (change in the metal grain size) were confirmed. As a result, in Cu, the grain size doubled, and the resistivity decreased by about 20%. In Ru, the grain size expanded by about 1.2 times, and the resistivity decreased by about 10%. This experimental evaluation was performed by a KrF excimer laser with a pulse width of 82 ns and was found to have the lowest resistance just before the irradiation damage threshold (melting or ablation initiation value) in both cases.

Keywords: 3D integration & packaging concerns: WtW/CtW bonding, Interposer, Through Si Via, CPI
Abstract: Cu to Cu direct bonding at low temperature has required the driving force of the Cu films to self-diffuse each other. In this study, high defect density Cu was optimized with a mechanical property of the self-annealing phenomena. Furthermore, the mechanism of the defect generation was studied with electrochemical analysis. Based on the analytical study, Cu to Cu bonding with the high defect density Cu, which had high tensile strength, was successfully conducted at 250℃ bonding temperature.

Keywords: 3D integration & packaging concerns: WtW/CtW bonding, Interposer, Through Si Via, CPI
Abstract: This study highlights different aspects and challenges of through silicon via (TSV) metallization in a via-last approach in thick Wafers. The TSV-last process enables a modular TSV integration in already existing technologies without major design or process changes. The study focuses on the challenges of the metallization process of the TSVs, including the metallization inside the TSV, the back side redistribution layer (RDL) as well as the contact to the front side metal. It is shown that the front side metallization has a significant influence on the TSV contact resistance. Furthermore, the influence of different electrolytes on the Cu-Plating process (used for TSV and RDL metallization) is analyzed.