Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Other Analog/RF Circuits and Systems
Abstract: This paper discusses alternative implementations of radio-frequency (RF) analog-to-digital converters (ADCs) by using bandpass delta-sigma modulators (BP-DSMs). Main architectural strategies, including the loop filter order, quantizer resolution, notch-frequency position, undersampling, and feed- back digital-to-analog converter (DAC), are overviewed, while considering their practical limitations in terms of system complexity, stability, dynamics and power consumption. Additionally, the combination of tunable notch-frequency and bandpass finite impulse response (FIR) filtered DAC is discussed as an efficient approach, offering reduced sensitivity to nonlinearities and clock jitter compared to the prior art.

Keywords: Converters, ADC, DAC and others
Abstract: This paper presents a fully dynamic discrete-time (DT) delta-sigma modulator (DSM) leveraging a floating inverter amplifier (FIA)-based dynamic loop filter and digital noise coupling (DNC) to enhance the power efficiency of the DT DSM for various sensor applications. Fabricated in a 28-nm CMOS process, the proposed architecture achieves 98.6-dB SNDR in 25-kHz bandwidth (BW), while consuming only 71.7 μW operating at 6.4 MS/s, resulting in Schreier Figure of Merit (FoMS) of 184 dB and Walden FoM (FoMW) of 20.6 fJ/conv.-step.

Keywords: Converters, ADC, DAC and others, Sensor Interface Circuits and Microsystems
Abstract: This paper presents a power-efficient, low-noise, and high-input-impedance continuous-time (CT) incremental ADC (IADC) suitable for interfacing multiplexed sensors. High quantization efficiency is achieved using a current-controlled-oscillator quantizer (CCOQ), which provides intrinsic dynamic element matching and an additional order of noise shaping. A Gm-C-based first integrator is used to boost the input impedance of the ADC to > 500 MΩ. By taking advantage of the low-pass signal transfer function of the IADC, chopping is incorporated into the first integrator stage. To reduce the quiescent current and noise of the Gm cell, a new reset timing scheme is proposed for the incremental operation with CCOQ. A prototype was designed and simulated in a 180 nm CMOS process. The ADC runs at a clock frequency of 1.6 MHz and has a Nyquist bandwidth of 12.5 kHz. Based on simulation results, the IADC achieves 87.9 dB SNDR, 89 dB dynamic range while consuming 115 uW of power. Overall, this approach demonstrates the possibility of using one incremental ADC for direct digitization of multiplexed biomedical and IoT sensors.

Keywords: Converters, ADC, DAC and others
Abstract: An incremental delta-sigma analog-to-digital converter (I-DS ADC) with a third-order hybrid CT/DT loop filter (LF) is presented. By employing a first-order CT integrator in the first stage, followed by second-order discrete-time (DT) integrators, the proposed ADC achieves high power efficiency while maintaining the easy driving and inherent anti-aliasing characteristics of a continuous-time (CT) delta-sigma modulator (DSM). To further improve power efficiency, a dynamically biased class-AB is proposed for the CT integrator, while a dynamic floating inverter amplifier (FIA) is utilized in the DT integrators. Input pre-conversion is adopted for fast settling of the LF, and by precisely coordinating the timing between the CT and DT LFs, accurate sample-by-sample operation is achieved. The proposed I-DS ADC was implemented in a 28-nm CMOS process, occupying 0.28 mm2, including the on-chip reconstruction filter. It achieves an SNR of 100.1dB, an SNDR of 97.1dB, in a 10kHz bandwidth, while consuming 505uW from a 1V supply. Measurement results indicate that the proposed hybrid I-ADC achieves a -40dB rejection for the input at the sampling frequency, demonstrating its anti-aliasing filtering (AAF) effect.

Keywords: Converters, ADC, DAC and others
Abstract: This paper presents a hybrid Current Source–Capacitor Digital-to-Analog Converter (DAC) that achieves high linearity with enhanced area efficiency. The proposed architecture combines compact MOS current sources and minimum-sized capacitors to reduce silicon footprint while maintaining high performance. A low-overhead digital calibration algorithm corrects nonlinearity due to mismatch, enabling precise compensation of large transfer function errors. A 14-bit prototype, implemented in TSMC 180 nm CMOS and verified through simulation, achieves INL/DNL within ±0.8/1.2 LSB post-calibration. Dynamic metrics, including SNR, SFDR, THD, and ENOB, show significant improvement, confirming design robustness. Monte Carlo simulations validate reliability under process and mismatch variations. This compact, high-resolution DAC is well-suited for dense IC applications, and its calibration strategy offers a scalable path for future high-performance mixed-signal systems.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Other Analog/RF Circuits and Systems
Abstract: 6G communication systems impose higher demands on the data sampling rate and linearity of digital-to-analog converters (DACs). This paper proposes a time-interleaved digitalto- analog converter (TI-DAC) design, applying tree-structured dynamic element matching (DEM) to TI-DAC, which significantly enhances the spurious-free dynamic range (SFDR). Simulation results in the Simulink environment demonstrate that the proposed TI-DAC with time-domain dynamic element matching (TDEM) improves both the data conversion speed and the SFDR of DACs, providing an effective solution for high-performance signal conversion in 6G communication systems.

Keywords: Neuromorphic System Algorithms and Applications, Neural Learning System Algorithms and Applications, AI Digital Hardware, Accelerators, and Circuits
Abstract: We propose a low-overhead reservoir computing framework using a combination of several techniques. For the main reservoir architecture, we explore Simple Cycle Reservoir (SCR) instead of the more commonly used Echo State Network (ESN). We explore five simplified nonlinear activation functions in addition to the more commonly used hyperbolic tangent function. We also include an additional hyperparameter for memory- nonlinearity tradeoff which dictates the proportion of linear and nonlinear activation functions. We use genetic algorithm for hyperparameter tuning and illustrate how reduced-precision arithmetic (16-bit) can be used to simplify hardware requirements while maintaining competitive performance. We have run extensive experiments on standard benchmarks for proposed techniques which demonstrate the potential of the proposed approach for low-overhead edge AI systems.

Keywords: Neuromorphic System Algorithms and Applications, Neuromorphic Circuits and Systems
Abstract: A novel digital Hindmarsh-Rose neuron was designed and implemented on FGPA. The proposed design outperforms previous implementations in terms of accuracy, digital resource consumption, and maximum clock frequency. These qualities make the proposed design a strong candidate for neuroscientific simulation. The proposed design requires only 368 Look-Up Tables to implement and operates at a maximum clock frequency of 373.55MHz.

Keywords: Neural Learning System Algorithms and Applications, Biomedical Signal/Image Processing, Neural Learning Circuits & Systems
Abstract: Transcranial focused ultrasound stimulation (tFUS) is a promising noninvasive neuromodulation technique that enables targeted brain stimulation with higher precision than other noninvasive methods. However, unknown parameters such as the geometry of the ultrasound (US) phased array (i.e., positions of US elements) particularly in flexible US arrays and variations in skull shape complicate accurate focusing and targeting in US beamforming through electronics. This study presents a deep learning framework using simulated backscattered RF signals to estimate the US array geometry and skull shape. Validated on 5,700 RF simulations, the framework achieved 99.55% training accuracy and 96.84% validation accuracy for array geometry estimation, and Dice scores of 93.99% (training) and 91.15% (validation) for skull segmentation. Testing on unseen datasets demonstrated robust spatial precision, with a mean Euclidean distance of 1.85 mm and strong precision, recall, and F1 scores.

Keywords: Neuromorphic Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: This paper presents the rapid prototyping of an analog spiking neuron for MNIST classification using hardware-in-the-loop to construct a convolution neural network (CNN). The neuron is implemented as a voltage-mode neuron using an op amp to perform time-domain integration of the synaptic inputs. The synapse is realized with a digital-to-analog converter (DAC) that modulates the input voltage spike magnitude by the synaptic weight. A switched-capacitor bank implements the feedback capacitor allowing a tunable constant of integration. A time-multiplexed approach emulates a fully parallel convolution neural network (CNN). The system employs commercial off-the-shelf components (COTS) to realize the neuron design, making it suitable for rapid, low-cost prototyping prior to full-scale integrated circuit (IC) implementation.

Keywords: Neuromorphic Circuits and Systems, Neural Networks and Fuzzy Logic, Neuromorphic Audio and Video Processing
Abstract: For event-driven audio processing, Stochastic Artificial Neural Networks (SANNs) present a viable substitute for conventional Convolutional Neural Networks (CNNs). Using a simplified surrogate event-based artificial cochlea, this study assesses a SANN’s capacity to identify musical chords in the presence of noise. A study on training noise was performed using (1) spatial-domain Gaussian noise and (2) frequency-domain noise. Spatial-domain noise generates artifacts that is shown to impair performance for some bitstream lengths. Frequency-domain noise training more accurately replicates real-world aberrations, and is show to be successful. Datasets with higher noise levels showed persistent convergence but decreased accuracy. These results demonstrate the potential of SANNs for reliable processing of auditory signals.

Keywords: Neural Networks and Fuzzy Logic, Implantable/injectable Systems, Artificial Intelligence for Complex Networks and Nonlinear Systems
Abstract: Effective blood glucose regulation is essential for Type-1 Diabetes Mellitus patients to maintain overall health and prevent complications. While Type-1 fuzzy logic controllers have shown promising results, they often struggle with handling uncertainties and variations in physiological responses. This paper introduces a closed-loop control system using a Mamdani Interval Type-2 fuzzy logic controller to improve blood glucose regulation. By incorporating uncertainty in membership functions, the proposed controller improves adaptability to patient-specific variations and external disturbances. The controller uses fewer membership functions compared to other works in this field, which reduces the number of rules and, consequently, the computational complexity. The controller is evaluated through multiple test scenarios, demonstrating its effectiveness in maintaining glucose levels within the safe range of 70–180 mg/dL. Hence, it also reduces the risk of both hypoglycemia and hyperglycemia. Simulations also show that this controller achieves the desired level faster, especially in scenarios with high meal disturbances.

Keywords: Digital Integrated Circuits, Other Digital Circuits and Systems, Digital Filters
Abstract: A counting network accepts n bits as inputs and produces m output bits, collectively representing a function of the number w of 1s among the n inputs. Examples include parallel counters (Hamming-weight determiners), parallel compressors, majority bit-voters, comparators, and various threshold functions. We show that a recursive formulation of such networks allows us to efficiently map them onto a 2D reconfigurable array of 2-input multiplexes, offering low-cost realizations and high-throughput, pipelined computation due to the availability of highly-optimized multiplexer circuits and VLSI regularity of the multiplexer array.

Keywords: Digital Integrated Circuits, Other Digital Circuits and Systems, Other Signal and Image Processing
Abstract: The design of approximate adders has been widely researched to advance energy-efficient hardware for computation intensive multimedia applications, such as image/audio/video processing. Several static and dynamic approximate adders exist in the literature, each of which endeavors to balance the conflicting demands of high performance, computational accuracy, and energy efficiency. This work introduces a novel approximate adder that is more energy- and area-efficient than existing adders, while achieving improved or comparable accuracy, as demonstrated by simulation results. The proposed adder’s ability to digitally reconstruct high-quality images is further demonstrated by the deployment of the design for an image processing task.

Keywords: Digital Integrated Circuits, Other Digital Circuits and Systems
Abstract: Posit has emerged as a dynamic floating-point representation that adapts its fractional size based on the numerical requirements, enabled by the additional regime field. A posit conversion unit ensures efficient format adaptation for hardware processing. This paper proposes parameterized architectures for posit conversion units with optimized regime and exponent computation with improved datapath efficiency and reduced hardware overhead. The architectures are validated for 16, 32, and 64-bit posits. Compared to existing architectures in terms of power-performance-area (PPA) overhead, the proposed work shows an improvement of 2–18% in resources and 6–37% in performance on FPGA devices. The post-synthesis PPA evaluation shows an improvement of 10–66% in area, 34–72% in delay, and 35–78% in power on the 28 and 45 nm technology nodes. Integrating the proposed architectures with the posit adder/multiplier modules improves the average area-power-delay product by 62.74/35.83% on 28/45 nm technology over state-of-the-art designs. The results validate the proposed parameterized architectures, demonstrating low-overhead, improved hardware efficiency, and scalable integration with arithmetic modules.

Keywords: Digital Integrated Circuits, Other Digital Circuits and Systems
Abstract: Stochastic computing (SC) is an approximate computing paradigm that uses stochastic numbers (SNs) representing the probability of a `1' appearing in a bit stream. In certain SC operations, a strong correlation between two SNs is necessary to improve computational accuracy. This paper refines a leading correlation enhancement algorithm by modifying the condition for determining the magnitude relationship when processing SNs sequentially. Moreover, by partially relaxing the conditions for bit replacement and introducing thresholds to control these conditions, more opportunities for correlation enhancement are created. Experimental results show that the proposed algorithm improves correlation and reduces output errors compared with the existing method, with small area overhead and negligible impact on delay. Power consumption increases moderately depending on whether one or both refinements are applied.

Keywords: Digital Filters, Other Signal and Image Processing
Abstract: We present a fast fully-pipelined scalable hardware design for kxk median filters based on the forgetful_selection algorithm, which does not need sorting, but rather finding the extrema. Results are presented in terms of resources and processing cycles. The design, validated on a FPGA, features a moderate increase in hardware resources as k (3,5,7,9,11) grows.

Keywords: Hardware-Software Co-Design, Embedded Processors and Controllers, Other AI and Edge Topics
Abstract: Point cloud is an important type of geometric data structure for many robotics or 3D applications such as Autonomous Driving, Augmented Reality (AR), and Virtual Reality (VR). Raw point clouds generated by 3D sensors are typically large-scale and irregular. For these reasons, most of point cloud applications require an expensive down-sampling pre-processing phase for the raw point cloud to regularize it. With the traditional down-sampling methods, this pre-processing phase often accounts for the majority of the end-to-end latency. Recently, the Octree-based pre-processing method has been proposed to efficiently perform the down-sampling phase. Building on this approach and the spatial proximity function of Octree nodes, we propose an Approximate Octree-Indexed Sampling (OIS) method to further accelerate Octree-based down-sampling and implement it as an FPGA-based accelerator, functioning as a near-sensor processor.

In our evaluation, using benchmarks from three popular point cloud datasets, we first present the theoretical workload savings (ranging from 27.3% to 50%) achieved through the optimization of the approximation method. We then demonstrate that, compared to the current Octree-based down-sampling accelerator, our FPGA-based prototype accelerator performing the Approximate OIS method achieves additional speedups ranging from 1.5x to 2.01x. Using point cloud AI benchmarks, we further demonstrate that the Approximate OIS method introduces close-to-zero loss in accuracy.

Keywords: Communications Circuits, Theory and Applications, Analog Circuits and Systems, Communications Systems and Control
Abstract: This work presents a 40-Gb/s four-level pulse amplitude modulation (PAM-4) driver implemented in 28-nm CMOS technology for a vertical-cavity surface-emitting laser (VCSEL). The reconfigurable 3-tap fractionally spaced feed-forward equalizer (FFE) compensates for the limited modulation bandwidth of a VCSEL. A thermometer encoder and a voltage-mode push-pull output driver with adjustable strength are employed to minimize the VCSEL optical response nonlinearity. The implemented driver achieves the energy efficiency of 3.7 pJ/bit and the bandwidth efficiency of 3.3 bit/Hz at 40-Gb/s PAM-4 signaling.

Keywords: Analog Circuits and Systems, Communications Circuits, Theory and Applications, Linear and Non-linear Analog Systems
Abstract: This paper presents a modular approach for equalizing chromatic dispersion (CD) in coherent optical transceivers. The approach employs a multistage analog feedforward equalizer (FFE) that realizes the correction capability of a contingent decision equalizer (CDE) assuming an infinite resolution quantizer. The pipelined structure enables streamlined tuning of number of active equalization stages to match prevailing inter-symbol interference (ISI) thereby reducing power consumption. Additionally, the modular architecture significantly reduces design complexity. The effectiveness of the proposed equalizer in mitigating the impact of CD is demonstrated using behavioral simulations at multiple data rates. This performance of the proposed equalizer using zero-forcing (ZF) is compared to the conventional FFE with ZF, minimum-mean-square-error (MMSE) and inverse channel methods. Superior receiver performance (1.50x eye height, 1.14x eye width and 1.34x better error vector magnitude (EVM)) is achieved in a 200 Gb/s 16QAM system, while providing energy-proportional data rate scaling.

Keywords: Digital Integrated Circuits, Digital Filters, Other Digital Circuits and Systems
Abstract: Baseline wander (BLW) noise introduced through AC-coupling in serializer/deserializer (SerDes) receivers significantly degrades signal integrity. This paper presents a fully digital baseline wander compensation (BLWC) methodology for ADC-based SerDes receivers. The compensation architecture performs critical information extraction and parallel-to-serial conversion at the front-end, while employing a loop envelope detection algorithm for BLW noise quantification. To enhance integrator response speed and mitigate loop latency effects, a shift-average filtering algorithm (sumfilt) utilizing noise characteristics is proposed. Furthermore, a simplified linearized model is developed to determine optimal loop gain and latency parameters. Behavioral-level simulations across multiple data patterns in a 32 Gb/s non-return-to-zero (NRZ) modulated SerDes system demonstrate the proposed compensation technique's effectiveness and robustness.

Keywords: Other Analog/RF Circuits and Systems, Communications Circuits, Theory and Applications, Other Wireless and Communications Topics
Abstract: A 16-Gb/s continuous-time linear equalizer (CTLE) is designed in 28-nm CMOS technology, featuring an active inductor load and feedforward compensation to enhance high- frequency performance. The proposed design features a power-efficient architecture, achieving a remarkable eye opening of 45.75 ps and a vertical differential eye opening of 781.19mV. The design achieves reliable operation for channel losses of 9dB, consuming a total power of 3.3 mW from a 0.9 V supply. This CTLE provides an energy-efficient solution for high-speed SerDes applications, with a calculated figure-of-merit of 0.022 pJ/bit/dB.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Converters, ADC, DAC and others
Abstract: This paper proposes a stochastic approach to extract the equalization parameters and pulse response of receiver equalization circuits that use unequalized decisions. Conventional lone pulse or single-bit response methodology assumes linear components and leads to suboptimal architecture definition for a new class of nonlinear multi-stage equalizers. The theoretical basis for the stochastic pulse response characterization is presented and time-domain simulations are used to show the efficacy of the approach in characterizing the equalized pulse response of a 1-tap contingent decision equalizer. Moreover, time-domain empirical performance simulations using MATLAB Simulink model of the receiver show significantly improved bit error rate performance with parameters extracted with the proposed approach, achieving 3.4x voltage margin compared to conventional

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Analog Circuits and Systems
Abstract: This paper introduces a new class of fractional- order phase-locked loops (FOPLLs) of complex orders, extending the traditional integer-order or even the real-order models. By incorporating fractional-order dynamics of complex orders into the loop filter (LF) and voltage-controlled oscillator (VCO), the proposed FOPLL demonstrates superior performance in terms of capture and locking time. The complex-order fractional calculus allows for a more flexible and adaptive design, improving the phase response and stability of the system with lower values of loop constants. Numerical simulations validate the effectiveness of the proposed FOPLL, showing significant improvements over both conventional integer-order or fractional real-order PLLs. The results highlight the potential of complex-order fractional calculus in improving the performance of phase-locked loops in various applications, including communication systems, signal processing, and control systems.

Keywords: Visible/Near-IR/IR Integrated Photonics, Analog, Digital and Mixed Signal Processing, Electronic/Photonic Integration
Abstract: This paper surveys the state of integrated microwave photonic circuits for application to wideband microwave and millimeter wave applications. We discuss current photonic integrated circuit technology and explore techniques for photonic signal processing and photonic signal conditioning for future microwave and millimeter wave systems.

Keywords: Visible/Near-IR/IR Integrated Photonics, Heterogeneous Integration, RF Front-End Circuits
Abstract: Similar to electronic multi-chip modules (MCMs), photonic MCMs (P-MCMs) integrate multiple chips onto a common substrate to provide benefits (e.g., performance, size, power consumption, yield) that cannot be achieved through monolithic, single-chip integration. We report the development of a novel P-MCM platform that integrates best-in-class photonic components (e.g., external-cavity lasers, thin-film lithium-niobate (TFLN) optical modulators, high-Q optical filters, balanced-waveguide photodiodes) onto a silicon-wafer “intermount” that facilitates efficient optical coupling between components and provides environmentally stable mechanical support. The performance demonstrated from the integrated components make the P-MCM platform a strong candidate for realizing microwave photonic (MWP) subsystems having radio-frequency (RF) performance superior to what can be achieved from discrete, fiber-pigtailed photonic components or other photonic integrated circuit (PIC) technologies. Other potential applications include optical interfaces for atom-based quantum computers and optical clocks, free-space lasercom, and remote optical sensing.

Keywords: Electronic/Photonic Integration, Analog Circuits and Systems, Communications Circuits, Theory and Applications
Abstract: We begin by reviewing three optical technologies (the worlwide optical network, integrated photonics, and frequency combs) that are poised to revolutionize land-based positioning, navigation and timing (PNT) by greatly reducing our dependence on the global position system (GPS) and other global navigation satellite systems (GNSS). To achieve this revolution a holdover clock with sufficient resolution must be developed. We describe the required elements in a holdover clock and an architecture that was proposed by colleagues at the Army Research Laboratory (ARL) in Adelphi, MD with collaborators at the University of Maryland Baltimore County (UMBC). Microresonator frequency combs are a key element in a holdover clock. We then describe work being carried out at UMBC in collaboration with scientists at other institutions including AIM-Photonics to advance the state-of-the-art in microresonator frequency combs for PNT applications.

Keywords: Analog Circuits and Systems, Electronic/Photonic Integration
Abstract: In this review, we cover recent progress in the development on-chip electro-optic modulators across a range of integrated photonics platforms. We focus on the subset of modulators that relies on the Pockels effect to modulate optical signals. The Pockels effect is characterized by a linear response to applied voltage and is not inherently associated with amplitude modulation, which makes it well-suited to the realization of modulators used in photonic-assisted microwave systems. However, Pockels effect-based modulators realized in integrated photonics span a variety of materials and device geometries, each with their own advantages and disadvantages. We explore the significance of modulator figures of merit and highlight how these metrics can guide the choice of modulator to meet prescribed system or mission requirements.

Keywords: Electronic/Photonic Integration, RF Front-End Circuits
Abstract: Wireless perception requires processing of broad-band spectrum by Artificial Intelligence (AI) pipelines. However, direct sampling of other electronics-only solutions is unsuitable for simultaneous processing of low-RF to FR3 band (24 GHz).

We propose combining CMOS electronic circuits with silicon-based photonic integrated circuits (PICs) to enable novel broadband RF photonic channelizers. This work presents a system-level design and analysis of a channelizer using on-PIC optical filter banks and optical-domain demodulation.

Keywords: Machine Learning at the Edge, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: Heart disease is one of the major causes of mortality worldwide and in USA. Heart sound signals recorded as phonocardiogram (PCG) provide valuable insights into cardiac health. This work presents a solution for monitoring user cardiac health and detecting abnormalities from PCG using artificial intelligence (AI) embedded into wearable for on-device monitoring. To meet the power and area constraints in wearable sensors, reservoir-computing is used as the AI module. An analog reservoir-computer (RC) test-chip fabricated in 28nm consumes 23.5nJ while detecting heart abnormalities with 88.2% accuracy.

Keywords: Integrated Biomedical Systems, Wearable Smart Sensor Systems, Secure AI Hardware
Abstract: Wearable and implantable healthcare sensors are pivotal for real-time patient monitoring but face critical challenges in power efficiency, data security, and signal noise. This paper introduces a novel platform that leverages hardware noise as a dual-purpose resource to enhance machine learning (ML) robustness and secure data via Physical Unclonable Functions (PUFs). By integrating noise-driven signal processing, PUF-based authentication, and ML-based anomaly detection, our system achieves secure, low-power monitoring for devices like ECG wearables. Simulations demonstrate that noise improves ML accuracy by 8% (92% for detecting premature ventricular contractions (PVCs) and atrial fibrillation (AF)), while PUFs provide 98% uniqueness for tamper-resistant security, all within a 50 µW power budget. This unified approach not only addresses power, security, and noise challenges but also enables scalable, intelligent sensing for telemedicine and IoT applications.

Keywords: Machine Learning at the Edge, AI-IoT Systems and Applications, AI Digital Hardware, Accelerators, and Circuits
Abstract: Diabetic foot ulcers (DFUs), a class of chronic wounds, affect ~750,000 individuals every year in the US alone and identifying non-healing DFUs that develop to chronic wounds early can drastically reduce treatment costs and minimize risks of amputation. There is therefore a pressing need for diagnostic tools that can detect non-healing DFUs early. We develop a low cost, multi-analyte 3D printed assays seamlessly integrated on swabs that can identify non-healing DFUs and a Wound Sensor iOS App - an innovative mobile application developed for the controlled acquisition and automated analysis of wound sensor data. By comparing both the original base image (before exposure to the wound) and the wound-exposed image, we developed automated computer vision techniques to compare density changes between the two assay images, which allow us to automatically determine the severity of the wound. The iOS app ensures accurate data collection and presents actionable insights, despite challenges such as variations in camera configurations and ambient conditions. The proposed integrated sensor and iOS app will allow healthcare professionals to monitor wound conditions real-time, track healing progress, and assess critical parameters related to wound care.

Keywords: Other Areas in Biomedical Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Integrated Biomedical Systems
Abstract: Real-time epileptic seizure detection and prediction demand low-latency, ultra-low-power, compact, and ideally batteryless computing near implanted electrodes. Machine Learning (ML) based detectors, offering superior accuracy, necessitate efficient on-sensor implementations for continuous edge monitoring. Although analog multiply and accumulate (MAC) operations for ML are known to consume 10X–100X less power than digital, they require analog-to-digital (ADC) and digital-to-analog converters (DAC) to prevent noise accumulation and propagation, which dominates the system level power consumption. We show that analog-to-time (ATC) and time-to-analog (TAC) converters in 65nm technology achieve 2.69X lower energy per 8-bit conversion than ADCs/DACs. A seizure detection model using analog circuits with ATCs, TACs, and layer-wise precision consumes 1.9X less energy than one using ADCs/DACs. To evaluate noise tolerance, we inject 0%–50% Gaussian noise into a model adapted for classifying pre-ictal and inter-ictal segments for five patients in the CHB-MIT dataset. For Patient 8, accuracy drops only sim1% with 10%–17% multiplicative noise; for Patients 1, 2, 3, and 5, the accuracy degradation is sim4%.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Machine Learning at the Edge, Neuromorphic Circuits and Systems
Abstract: Digital twins (DTs) can enable precision healthcare by continually learning a mathematical representation of patient-specific dynamics. However, mission critical healthcare applications require fast, resource-efficient DT learning, which is often infeasible with existing model recovery (MR) techniques due to their reliance on iterative solvers and high compute/memory demands. In this paper, we present a general DT learning framework that is amenable to acceleration on reconfigurable hardware such as FPGAs, enabling substantial speedup and energy efficiency. We compare our FPGA based implementation with a multi-processing implementation in mobile GPU, which is a popular choice for AI in edge devices. Further, we compare both edge AI implementations with cloud GPU baseline. Specifically, our FPGA implementation achieves an 8.8× improvement in performance-per-watt for the MR task, a 28.5× reduction in DRAM footprint, and a 1.67× runtime speedup compared to cloud (mobile) GPU baselines. On the other hand, mobile GPU achieves 2x better performance per watts than FPGA but has 2x increase in runtime and 10x more DRAM footprint than FPGA. We show the usage of this technique in DT guided synthetic data generation for Type 1 Diabetes and proactive coronary artery disease detection.

Keywords: Other Sensory Circuits and Systems, RF Front-End Circuits, Other Analog/RF Circuits and Systems
Abstract: This research investigates a tree-search algorithm for transmitter beam forming as an approach for efficient target detection in cognitive radar systems. Key performance metrics such as detection probability, false alarm rate, and energy efficiency are derived to evaluate the efficacy of this adaptive search strategy in the application scenario of a drone performing target detection so that it can find open spaces and avoid collisions. Results indicate that the tree-search approach exhibits improved computational efficiency and faster response times compared to traditional scanning methods. The findings underscore the importance of algorithmic design considerations when addressing trade-offs between accuracy and resource utilization in radar systems. This analysis establishes that tree search in transmitter beam forming is a fast and power-efficient method for detecting targets when the downstream computational costs are high or when the environment is sparse.

Keywords: Point-of-Care Biomedical Diagnostics, Lab-on-CMOS and Lab-on-Chip, Integrated Biomedical Systems
Abstract: Point-of-care diagnostic devices enable rapid disease detection but can require labor-intensive fabrication. Reagents used in lab-on-a-chip devices can be in liquid form stored in blister packs or in freeze dried form which is made using the method of lyophilization. Preparation of reagents for lyophilization and placement into microfluidic chips can be more time consuming than their liquid counterparts. This study automated the lyophilization process for microfluidic chip reagents by designing a 3D-printed rig to eject and transfer frozen reagent shapes. The device was evaluated for efficiency and ability to retain reagent integrity by comparing it with established manual removal methods. The experiments demonstrated reduced handling time, improved reproducibility, and minimized reagent loss. In general, the rig was three times faster at removing reagent shapes than manual methods (p<0.001). These outcomes support efficient reagent preparation, therefore enhancing the reliability of diagnostic device fabrication

Keywords: Point-of-Care Biomedical Diagnostics, Lab-on-CMOS and Lab-on-Chip, Integrated Biomedical Systems
Abstract: Point-of-care devices are used to deliver medical diagnostics straight to patient locations. Therefore, these devices must be easy to use for healthcare providers and users in various environments. For some devices, syringes are required for proper use; however, these syringes can be difficult to use and inhibit the device’s usability. A proposed solution to this problem is replacing the syringes holding regents with blister packs, which can be easily punctured with a small force. A layered test chip, blister holder, and blister packs were created to test the liquid transfer efficiency of blister packs. These blister packs were made from plastic thermoformed sheets, foil, and adhesives. Blisters for 200, 250, 300, and 350 µL were created, with corresponding base diameters of 8.84, 9.75, 10.57, and 11.32 mm, respectively. Blister packs integrated into the test chip retained an average of 55% of reagent across 40 trials, with retention ranging from 45% to 80% depending on volume. While ANOVA results did not show statistical significance in liquid transfer (p=0.62), 300 µL blisters exceeded theoretical expectations in over 75% of trials, showing an acceptable volume for usability. Although blister packs were effective for on-chip reagent storage, variability in delivery efficiency across blister sizes indicates a need for further optimization through improved design, material selection, and actuation methods. This work establishes a foundation for standardizing blister-based fluid delivery, with potential implications for low-cost diagnostics in remote settings

Keywords: Wearable Smart Sensor Systems, Sensor Interface Circuits and Microsystems, Bio-signal Amplifiers
Abstract: This paper addresses the urgent need for advanced health monitoring solutions tailored for next-generation smart screening and diagnostics. We propose a novel approach utilizing a lightweight, low-power, and cost-effective wearable patch, designed to overcome the limitations of traditional bulky sensing units. Our innovative design features a flexible electrode grid with minimized wiring, integrated sensor readout electronics, and inkjet-printed spiral coils, enabling efficient wireless charging. The electrode grid manifests an array of sensing pads encircled by a reference terminal, which can be selectively excited by a constant potential. The electrode grid measures the impedance between the sensing pad and the reference ring and generates a current proportional to the sensing material. The sensor current is then passed through a multichannel inverting amplifier to generate the output signal. The printed spiral coils work in resonant mode to couple power from an external source to the wearable patch to power up the electronics. This work aims to provide a practical and affordable solution for real-world health monitoring applications, paving the way for widespread deployment in diverse settings.

Keywords: Sensor Interface Circuits and Microsystems, Sensor Fusion
Abstract: We consider the problem of target ranging at very short distances using free space frequency-modulated continuous wave (FMCW) LiDAR with single pixel imaging. This is a challenging problem due to the presence of phase noise and environmental factors that reduce precision of measurements made at short ranges. We present a novel technique for free space FMCW LiDAR with single pixel imaging that uses a dual path-based setup to mitigate the noise. Experimental results from laboratory setups with different target ranges show that this technique is able to perform precise measurements at short ranges while introducing very little noise.

Keywords: In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Other AI and Edge Topics
Abstract: Traditional computing architectures struggle to keep up with modern neural networks due to energy consumption and processing speed limitations. To address these challenges, we propose MAKAN, a framework that integrates Kolmogorov-Arnold Networks (KANs) with the BITLITE memristor-based computing platform. KANs, which use learnable activation functions on edges instead of fixed functions on nodes, offer superior flexibility and accuracy, but their reliance on spline-based functions limits scalability. MAKAN overcomes this by using hat functions for piecewise linear (PWL) function approximation, efficiently implemented on BITLITE’s bit-wise memristor crossbars for matrix-vector multiplication (MVM). By employing machine learning to reconstruct KAN’s spline functions with PWL on memristor circuits, MAKAN significantly reduces computational overhead while preserving accuracy and interpretability. This integration results in notable improvements in energy efficiency and processing speed, making advanced neural networks more scalable and practical for real-world applications, paving the way for future advancements in energy-efficient machine learning systems.

Keywords: AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, In-Memory Computing Circuits and Systems, Machine Learning at the Edge
Abstract: In this paper, we present a novel hybrid computing architecture designed to accelerate inference in 1-bit large language models (LLMs). Our approach combines the strengths of analog in-memory computing (IMC) and digital systolic arrays to address the diverse precision requirements across different layers of 1-bit LLMs. Specifically, we utilize analog IMC to accelerate low-precision matrix multiplication (MatMul) operations within the projection layers, which are naturally amenable to extreme quantization. Meanwhile, digital systolic arrays are employed to efficiently handle high-precision MatMul operations in the attention heads, preserving accuracy where precision is most critical. By partitioning the computational workload based on precision needs, our hybrid architecture increases throughput and energy efficiency. Experimental evaluations demonstrate that our design delivers up to an 80X improvement in tokens processed per second and achieves a 70% increase in energy efficiency (tokens per joule) when compared to conventional digital hardware accelerators.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Machine Learning at the Edge, AI-IoT Systems and Applications
Abstract: Miniature DNA sequencing hardware has begun to succeed in mobile contexts, driving demand for efficient machine learning at the edge. This domain leverages deep learning techniques familiar from speech and time-series analysis for both low-level signal processing and high-level genomic interpretation. Unlike audio, however, nanopore sequencing presents raw data rates over 100X higher, requiring more aggressive compute and memory handling. In this paper, we present a CMOS system-on-chip (SoC) designed for mobile genetic analysis. Our approach combines a multi-core RISC-V processor with tightly coupled accelerators for deep learning and bioinformatics. A hardware/software co-design strategy enables energy-efficient operation across a heterogeneous compute fabric, targeting real-time, on-device genome analysis. This work exemplifies the integration of deep learning, edge computing, and domain-specific hardware to advance next-generation mobile genomics.

Keywords: Neuromorphic Circuits and Systems, Embedded Processors and Controllers, Biomedical Signal/Image Processing
Abstract: This paper presents a lightweight spiking neural network (SNN) application for EMG-based hand gesture classification, demonstrating greater suitability over artificial neural networks (ANNs) for low-power, real-time neuromorphic processing applications. The compact SNN architecture is ideal for embedded machine-learning applications, such as portable medical devices. In this paper, we demonstrate two SNN networks, A and B. Each network was deployed and physically tested on an embedded system powered by the ARM Cortex-M4. Network A is trained and evaluated on the Roshambo dataset, while Network B is trained and evaluated on the CapgMyo dataset. Network A achieved an accuracy of 78.89%, and Network B achieved an accuracy of 70.83% on hardware, highlighting the potential for real-time, low-power EMG analysis in wearable devices.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Hardware-Software Co-Design, Machine Learning at the Edge
Abstract: 卷积神经网络 （CNN） 已广泛用于各种实际应用，例如图像检测、分割和姿态估计。但是，它们的密集计算和高频内存访问限制了在资源受限环境中的实现。最近的研究采用稀疏特性来消除零值计算，从而提高计算效率。在本文中，我们针对边缘设备提出了一种具有超稀疏计算引擎的节能型 CNN 处理架构。具体来说，为了实现基于位宽限制的稀疏性增强，开发了一种面向硬件的算法范式，它减少了 CNN 处理中弱贡献值的计算。此外，基于这一范式，提出了一种处理元素，通过重排内存访问方法有效支持超稀疏处理并减少内存访问。最后，在智能图像处理任务上的实验表明，所提出的架构在保持性能的同时，将乘法累加 （MAC）作减少了高达 79.98%，

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems
Abstract: Abstract—The Finite Impulse Response Digital-to-Analog Converter (FIR DAC) is an effective solution for suppressing clock jitter in Continuous-Time Delta-Sigma Modulators (CT-DSMs) while maintaining low power consumption. However, its application in Discrete-Time (DT) DSMs has been limited. In this work, we demonstrate that the FIR DAC not only mitigates mismatches between the two sampling capacitors in different branches of a double-sampled DT-DSM but also reduces the slew rate (SR) requirements of the integrator, leading to significant power savings. Despite these advantages, the use of an FIR DAC increases the complexity of the mismatch shaping circuit. To address this challenge, we employ noise-shaping segmentation, which optimizes power efficiency in the mismatch mitigation circuit. The proposed architecture is implemented using a cascade of integrators with feedforward (CIFF) configuration, achieving a 20 kHz bandwidth. Simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) of the analog-to-digital converter (ADC) reaches 108.6 dB, with a total power consumption of just 1.07 mW.

Keywords: Converters, ADC, DAC and others, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: This paper proposes a new type of neuromorphic analog-to-digital converter: a neuropredictive successive approximation register analog-to-digital converter (SAR ADC). By estimating the next input value using a neuromorphic predictor, the conversion time of a modified SAR ADC - and thus the energy consumption - can be reduced. In a preliminary investigation, a demonstrator designed for audio signals shows a 41.09% reduction in energy consumption compared to conventional SAR sampling. This ADC architecture proposes an alternative for ultra-low power applications.

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems
Abstract: This paper presents a three-segment interpolating digital-to-analog converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity and area efficiency. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment introduces a split unit resistor structure (rA,rB) to reduce post-calibration differential non-linearity (DNL), while the ISB employs redundancy-based interpolation, reducing voltage step errors while maintaining accuracy. A fully digital calibration algorithm is implemented to compensate for process variations, mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180nm CMOS process and is segmented into three parts: a 5-bit MSB section, a 5-bit ISB section, and a 6-bit LSB section. The proposed structure achieves worst-case post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) of less than ±1 LSB. Simulation results validate the design, demonstrating improved linearity and reduced area overhead compared to conventional segmented architectures.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Signal Processing Theory and Methods
Abstract: We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random timing mismatches among current sources. To decode the DAC input codewords into corresponding DAC switches, we present three algorithms with varying computational complexities. We perform high-level Matlab simulations to illustrate the dynamic performance improvement over the segmented structure.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Analog, Digital and Mixed Signal Processing
Abstract: 6G communication systems impose a higher demand on the linearity of digital-to-analog converters (DACs). Due to their excellent ability to eliminate non-linear distortions, tree-structured dynamic element matching (DEM) schemes, including fully segmented and highly segmented dynamic DEM, are expected to be used in DACs of 6G communication systems. This paper uses a 4-bit digital-to-analog converter (DAC) as a case study to evaluate and compare the input range, power consumption, and circuit complexity of fully segmented and highly segmented DEM DACs. Additionally, it provides comprehensive comparison and area-power tradeoff analysis of fully segmented and highly segmented DEM DACs with 8-bit, 10-bit, 12-bit, and 14-bit resolutions.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Other Analog/RF Circuits and Systems
Abstract: Fast FPGA-based arbitrary waveform generators (AWGs) are crucial for both quantum information science and technology (QIST) and classical communications. However, commonly used FPGA boards are limited to operating ranges of hundreds of MHz while tens of GHz are required. Consequently, more work is needed to bridge this gap. This paper describes a programmable analog-digital pulse generator that combines a FPGA board, which is used as a multi-channel arbitrary digital pattern generator in the GHz range, with a custom analog pulse generator. A pulse generator board based on step recovery diodes (SRDs) is shown to generate output pulses with nominal durations as short as 75 ps. An integrated pulse generator in 28 nm CMOS technology is also designed to obtain higher repetition rates (up to several GHz) and shorter pulse durations (15 ps).

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: In this paper, a ping-pong auto-zero correction feedback (AZCFB) loop for a chopper operational amplifier (op-amp) is demonstrated. The core structure of the op-amp is a chopper design, which is used to reduce low-frequency flicker noise. Additionally, a ripple suppression loop (RSL) is applied to eliminate the ripple introduced by the first stage of the op-amp. To prevent the offset voltage of the RSL from introducing ripple into the amplifier, a ping-pong auto-zero structure is used to cancel the offset voltage, especially that generated by the first stage of the RSL. Furthermore, a high-pass filter (HPF) is employed to isolate the DC signal at the sampling node from the AZCFB loop, thereby avoiding its influence and improving the accuracy of the AZCFB. Finally, the high-precision op-amp with AZCFB is implemented in a 0.18 µm CMOS process. Characteristics of the amplifier presented include rail to rail input and output operating on supplies of 1.8 to 5.5 V over -40 ℃ to 125 ℃. Quiescent supply current is 420 µA, achieving a maximum ripple of 3.9 µV, an offset voltage of less than 2.5 µV, and a noise power spectral density (PSD) of 10 nV/√Hz at 1 kHz.

Keywords: Analog Circuits and Systems
Abstract: This paper present a power-efficient operational amplifier (op-amp) architecture that simultaneously enhances DC gain and slew rate without sacrificing gain-bandwidth product (GBW), phase margin, or power efficiency. The proposed design incorporates a gain enhancement circuit that increases output resistance through a flipped voltage follower configuration, and a slew rate enhancement (SRE) circuit that activates only during large signal transitions. This adaptive biasing approach ensures low quiescent power consumption while delivering high dynamic performance. Implemented in the TSMC 180nm CMOS process, the op-amp achieves a 1650% improvement in slew rate and a 52 dB gain increase, operating with only 8 μA of supply current. Simulation results confirm the design maintains robust stability and outperforms previously reported state-of-the-art solutions.

Keywords: RF Front-End Circuits, Mixed-Signal RF and Baseline Circuits, Communications Circuits, Theory and Applications
Abstract: The digital switch-capacitor power amplifier (SCPA) suffers from the harmonics distortion which results in degraded out-of-band (OOB) suppression and the communication quality. This paper proposes a method that features variable amplitude control word (ACW) in one local oscillator (LO) cycle to eliminate the third-order harmonic with a single-ended architecture. The method reduces the number of the arrays and the total capacitors dynamic power consumption, while avoiding the mismatch of multiple arrays. The circuit simulation based 28nm CMOS process was conducted to validate the effectiveness. The results demonstrate a peak output power of 14 dBm and 52% efficiency at 2.4 GHz LO, with second- and third-order harmonics suppressed to 66 dBc and 53 dBc, respectively.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, RF Front-End Circuits
Abstract: Negative feedback in analog circuits is used to stabilize system response to device variations arising from manufacturing, aging, and temperature changes. Since its introduction, feedback analysis has focused on the innate device forward transfer property (transconductance) leading to a misinterpretation of key variables and conceptual properties. A feedback ‘loop’ was imagined which led analysis in the direction of describing this loop. In this paper a simple and unifying analysis is presented where interacting elements are identified and properly combined to describe the feedback return signal as a component of a port admittance, and manipulated to show the loop gain function fully accounting for loading, feedforward paths both in the external and internal to the active element, a single device or amplifying subcircuit. And the idea of ‘loop’ is corrected to lie in the math rather than directly in the circuit.

Keywords: Other Analog/RF Circuits and Systems
Abstract: This work presents a novel configurable hysteresis Schmitt trigger for Automotive Grade-1 General-Purpose Input-Output (GPIO) applications. The proposed circuit is designed using the GF 22FDXTM process technology. The Schmitt trigger thresholds, VH and VL can be configured either through externally applied control voltages or via internally generated ones. The hysteresis range is adjustable from 300 mV up to 1.5 V, with the observed VH and VL values being 1.25 - 3.1 V and 0.3 - 1.0 V, respectively. This proposed circuit is compact, with an area measuring 29.54×18.925 μm2. The dynamic power consumed is 280 μW, whereas the leakage power is 1.25 nW.

Keywords: Neural Learning System Algorithms and Applications, Wearable Smart Sensor Systems, Integrated Biomedical Systems
Abstract: This paper introduces a neural network-based calibration for low-force sensors that operate in the sub-newton regime (0-1 N) for wearable applications. The proposed calibration utilizes a fully-connected neural network to digitally reduce the sensor nonlinearity. The neural network is trained using data from a custom low-force measurement system with a novel compliant mechanism. Detailed study explores the trade-offs between the neural network size and activation function with calibration accuracy. Measurement results demonstrate four orders of improvement in the pressure sensor linearity, achieving errors less than 0.005 N. The proposed calibration is well-suited for wearable applications requiring precise low-force measurements.

Keywords: Neural Learning Circuits & Systems, Machine Learning at the Edge, Neuromorphic Circuits and Systems
Abstract: Keyword spotting (KWS) has become a crucial component of human-computer interaction with the advancement of artificial intelligence. To meet real-time demands, KWS systems must operate continuously with minimal area while maintaining high accuracy. However, traditional methods, including speech feature extraction algorithms and convolutional neural network (CNN), are computationally intensive and require significant processing power. In response to these challenges, we propose an SNN-based (Spiking Neural Network) keyword spotting algorithm that improves accuracy and reduces the area of the chip. The Neural Network Accelerator utilizes SNN to address the high bandwidth requirements of systolic array. This paper proposes a novel systolic spiking network architecture that enables SNN to perform computations within a systolic array. We also present the design of the corresponding circuit to implement key components of the network, such as the systolic spiking array, facilitating efficient hardware realization of the proposed architecture.

Keywords: Neuromorphic Circuits and Systems, Emerging Memory and Memristor, Converters, ADC, DAC and others
Abstract: Metal-oxide memristors, including HfO2, provide programmable memory based upon the actuation of a NFET gate in a 1T1R configuration. For computation, a digital-to-analog converter (DAC) modulates this gate with a fixed resolution. In this paper, a dynamic R-2R based DAC provides varying resolutions when setting the weights of the 1T1R synapse. This particular design allows the implementation of four binary resolutions with which to program the memristor, which can be independently set for each cell of the DPE. By setting the load of a current source, the device can achieve normal operation across multiple binary ranges simultaneously. Our proposed design shows a dynamic bit-resolution adaptation for a memristive architecture in a 65nm process.

Keywords: Neuromorphic Circuits and Systems, Other Neural and Neuromorphic Circuits and Systems Topics, Other Beyond CMOS Topics
Abstract: Abstract—This paper presents a carbon nanotube field-effect transistor (CNFET)-based full-swing reconfigurable spiking neuron for ultra-low-power neuromorphic computing. Building on the prior FSR-SN architecture implemented with CMOS, this design leverages the ballistic transport and electrostatic advantages of CNFETs to overcome the energy and scaling limitations of traditional MOSFETs. The proposed neuron implements the Integrate-and-Fire model using only seven transistors, eliminating the need for external capacitors by utilizing intrinsic parasitic capacitance. Designed at the 32 nm node with (17,0) chirality CNFETs, the neuron achieves a spiking frequency of 31.25 GHz and energy consumption of just 12.81 attojoules per spike. Only simulation was performed, with all results validated by transient analysis using the Stanford CNFET model in Cadence Virtuoso. This transition from CMOS to CNFET technology yields a 38× improvement in energy efficiency (482 aJ → 12.81 aJ) and over 20× spiking frequency boost (1.54 GHz → 31.25 GHz). Comparative benchmarks with neurons based on CMOS, Z2FET, SOI, and PD-SOI demonstrate significant improvements in energy efficiency and spike quality. This compact and reconfigurable architecture is well suited for scalable neuromorphic systems in edge AI, biomedical sensing, and robotics.

Keywords: Neuromorphic Circuits and Systems, Emerging Memory and Memristor, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: This work evaluates the performance of ferroelectric field-effect transistors (FeFETs) and memristors as nonvolatile memory (NVM) elements for time-domain (TD) neuromorphic computing. Key metrics considered include energy per operation, throughput, mismatch sensitivity and cell area. We use our high-efficiency TD computing cell as the platform for this analysis. Simulations indicate that FeFET-based implementations achieve operating frequencies exceeding 30 MHz while occupying only 33% of the area of an equivalent memristor-based circuit, though with higher energy consumption. The three-terminal nature of the FeFET also offers performance advantages that two-terminal memristor-based implementations can only replicate through more complex cell architectures. These performance benefits, along with their compatibility with existing CMOS processes, position FeFETs as a strong candidate for neuromorphic TD computing applications.

Keywords: Neuromorphic System Algorithms and Applications, Sensor Fusion, Other Signal and Image Processing
Abstract: This study presents a simple neural network model that simulates, in MATLAB, grid-cell-like activity and interprets location data in a 1D-axis environment. By encoding spatial information through overlapping Gaussian distributions of simulated grid cell firings, the model produces activation patterns that are then processed by an artificial neural network to train it to predict location based on these firing patterns. Simulation results demonstrate that the model achieves high accuracy in predicting location, with performance influenced by factors such as hidden layer size, varying use of grid cells, the number of location outputs, and the introduction of noise into the grid cell data.

Keywords: Digital Integrated Circuits
Abstract: GPS is becoming increasingly important for many applications, due to their precise positioning, navigation, and timing capabilities. The signals broadcasted by satellites are often quite weak and extremely susceptible to interference. Hence, the need for robust GPS receiver hardware. Many GPS systems (e.g., on UAVs) are deployed on resource-constrained embedded devices. In this paper, we propose an HLS-based FPGA hardware accelerator for image feature extraction of GPS interference signals, on embedded systems. Our HLS-FPGA hardware achieves up to 8.2x speedup compared to its software counterpart.

Keywords: Digital Integrated Circuits, Signal Processing Theory and Methods, Communications Circuits, Theory and Applications
Abstract: Orthogonal Frequency Division Multiplexing (OFDM) is a widely used modulation technique in communication systems, known for its robustness against channel impairments and high spectral efficiency. In this paper, a novel OFDM processor generator consisting of sample, symbol, and block processing functions, is presented using the agile design methodology based on Chisel hardware design language. The generator is capable of producing a wide range of processor instances from high-performance to low-cost configurations, supporting various parameter settings, such as error-correction coding/decoding, FFT size, modulation and interleaving schemes, sample rate, word length format and so on. By comparative analysis of the power-performance-area (PPA) metrics for each instance generated from varying parameters, near-optimal parameter configurations are identified to meet different application requirements. Once the hardware is configured, the generated OFDM processor can be reconfigured at the runtime to support any OFDM processing with less stringent requirements than the hardware configuration. Simulations of the synthesizable Verilog code emitted by the OFDM processor generator and FPGA implementations have demonstrated that the presented generator can not only accelerate the design process but also produce competitive instances tailored to diverse communication system needs.

Keywords: Digital Integrated Circuits, System on a Chip (SOC) and Network on a Chip (NOC), Other Digital Circuits and Systems
Abstract: Since design team produces design implementations by using standard cells of primitive logic gates that respect the design technology co-optimization (DTCO) parameter values provided by process team, it is essential to automate the generation of high quality standard cells to support the requirement of intensive DTCO iteration to find optimal parameter values. In this context, this paper surveys a recent research activities on the automation of standard cell layout generation at advanced FET technologies. Specifically, the research activities on automating standard cell generation surveyed in this paper are (1) the automation of generating diverse structures of standard cells of FinFET and Nanosheet-FET (NS-FET) devices, (2) the automation of generating Complementary-FET (CFET) based standard cells, and (3) the automation of generating Flip-FET (FFET) based standard cells.

Keywords: Digital Integrated Circuits
Abstract: Dual-output look-up tables (LUTs) are supported by modern commercial Field-Programmable Gate Array (FPGA) architectures. Existing technology mapping usually generates dual-output LUTs by merging single-output LUTs. However, these mapping solutions often fail to fully leverage the dual-output capability. This paper introduces a novel FPGA mapping scheme for dual-output look-up tables (LUT), designed to improve synthesis performance significantly. By introducing new metrics functions, kl-cut generation method, and methods to add secondary LUT outputs, the proposed approach enables thorough exploration of the design space. Synthesis results show that the proposed method achieves 30.2% and 32.0% improvement in LUT usage and depth when mapping dual-output LUTs, outperforming leading-edge mapping tools.

Keywords: Digital Integrated Circuits, Digital Filters
Abstract: This paper explores gate-level modeling and simula- tion of Single Event Transient (SET) filters in digital circuits. It demonstrates the feasibility of evaluating SET filter performance using gate-level simulations with the Skywater 130nm PDK, providing faster analysis than SPICE while maintaining sufficient timing accuracy.

Keywords: Digital Integrated Circuits, Hardware-Software Co-Design
Abstract: Number theoretic transform (NTT) is a critical operation in several post-quantum cryptography (PQC) schemes, which enables fast polynomial multiplication. However, it constitutes a significant portion of the total computational time in PQC schemes, requiring custom hardware accelerators. Manual register-transfer level (RTL) coding often requires re-designing memory structures and control units when configurations change. In contrast, the high-level synthesis (HLS) approach offers higher design abstraction, reducing development and verification time. This paper provides a comprehensive review of recent HLS-based NTT implementations, presenting their design strategies and comparing hardware resource utilization and performance on field programmable gate array platforms. Finally, the paper discusses potential future research directions to narrow the performance gap between RTL coding and HLS approaches.

Keywords: Processor and Memory Design and Architectures, Other Digital Circuits and Systems, Image, Video and Multi-Dimensional Signal Processing
Abstract: Ever since the Integrated Circuit was used in the Apollo Guidance Computer, which helped put man on the moon, computers have evolved into different forms to meet various requirements. Hardware accelerators are one such evolution in the realm of computing. They represent specialized hardware components designed to execute specific tasks more efficiently than traditional general-purpose processors. Combining the powers of both general-purpose processors and hardware accelerators is a bleeding-edge research area called heterogeneous computing. Advancements in 3D vision technology today demand faster computation on an unprecedented scale. Shape registration is one such operation predominantly carried out by an algorithm called iterative closest point (ICP). It is a computationally intensive algorithm with a lot of inherent parallelism, making it a suitable candidate for hardware acceleration through heterogeneous computing. In this article, we present our implementation of ICP in DPC++, a latest heterogeneous computing C++ compiler. A speedup of 24.66X and 35.59X were achieved by our CPU-GPU implementations, bruteforce-ICP and KD-tree ICP, respectively, compared to the CPU implementation on the Stanford bunny model point cloud - 35k resolution. Additionally, our GPU implementation of KD-Tree ICP is 2.6 times faster than the widely used state of the art ICP implementation by the Point Cloud Library.

Keywords: Machine Learning and Cognitive Radio, 5G & 6G Circuits and Systems, Other Digital Circuits and Systems
Abstract: The performance of fifth-generation (5G) coding techniques, such as low-density parity-check (LDPC) codes, is significantly affected by the error floor, which occurs in high signal-to-noise ratio (SNR) regions. Federated transfer learning (FTL), with its ability to learn from distributed data, can effectively improve error correction in low-SNR environments and extract crucial decoding features for high-SNR conditions. This paper introduces a two-stage decoding method that integrates layered LDPC decoding with FTL to mitigate the error floor and enhance system performance. Experimental results demonstrate that this approach significantly reduces error rates and improves decoding efficiency.

Keywords: 5G & 6G Circuits and Systems, RF Front-End Circuits, Other Analog/RF Circuits and Systems
Abstract: This work demonstrates the design of two classes of two stage high efficiency power amplifiers (PA) : the n-FinFET and the p-FinFET based capacitively neutralized architectures for next generation 5G FR2 mobile applications targeting 47GHz-48GHz (the n262 band). A link budget analysis of the transmitter in a system simulator is carried out to determine block level specifications while adopting IC, package and PCB floor-planning and thermal challenges early in the design. The two PAs are implemented on a Samsung 14nm FinFeT process as part of a broader implementation of a Front End module (FEM) co-designed with an Antenna on Package (AiP). The n-FinFET PA shows a small signal gain of 22dB in initial measurements, showcasing excellent correlation with simulation. Driven by comparable dc, small and large signal performance at a device level, the P-FinFET PA shows similar performance to the n-FinFET variant and is proposed here as a viable alternative for more reliable, high efficiency power amplification at mmWave for emerging cellular applications.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, RF Front-End Circuits, 5G & 6G Circuits and Systems
Abstract: This paper presents an 18.87–24.19 GHz dual-core, dual-mode voltage-controlled oscillator (VCO) using a multi-tap (MT) inductor-based 2-port resonator with capacitive coupling via a mode-switching block. The 2-port resonator introduces a gate-to-drain phase shift, suppressing flicker phase noise (PN), while the high-quality factor of the tank minimizes thermal PN. The mode-switching block enables dual resonance modes—high-frequency band (HB) and low-frequency band (LB), achieving a wide frequency tuning range (FTR) and low PN in both the 1/f^2 and 1/f^3 regions. The proposed VCO is implemented in 65 nm CMOS, and post-layout results show a PN of –68.7 dBc/Hz at a 10 kHz offset and –118.2 dBc/Hz at a 1 MHz offset from an 18.87 GHz carrier frequency, with a power consumption of 25.65 mW and an area of 0.154 mm^2. The peak figure of merit (FoM) is 189.6 dBc/Hz, and the maximum 1/f^3 noise corner frequency is 347 kHz across the FTR.

Keywords: Communications Systems and Control, Wireless Charging and Energy Harvesting, Other Wireless and Communications Topics
Abstract: Wireless networks utilize Cooperative Automatic Repeat Request (C-ARQ) protocols to enhance reliability. A key element of these protocols is selecting the appropriate node for retransmission to optimize performance. While various node selection criteria have been proposed, limited attention has been given to implementing distributed criteria. Therefore, this paper proposes a practical method for implementing distributed node selection criteria in a network of multiple energy-harvesting nodes and a base station. While we apply this method to a criterion that focuses solely on the current energy levels of the nodes, given our emphasis on energy harvesting wireless networks, the method can be easily adapted to other criteria, such as those that also consider channel conditions. The results show that the proposed method performs as expected. However, the method cannot prevent duplicate transmissions caused by nodes having the same or relatively close energy battery levels.

Keywords: RF Front-End Circuits, Other Analog/RF Circuits and Systems, 5G & 6G Circuits and Systems
Abstract: This paper presents a high-performance phase shifter based on a Vector-Modulator (VM) topology operating at 39-GHz center frequency with a 35-49 GHz 3dB-bandwidth (BW). The proposed VM consists of a quadrature hybrid followed by variable-gain amplifiers (VGAs). The quadrature hybrid uses a two-stage transformer-based topology which maximizes the VM gain, and the VGAs are based on parallel Gm cells designed to keep the current density constant, and hence, maintain constant gain performance across the phase circle. The phase shifter is fabricated in 45nm CMOS SOI technology and the average measured gain is 2.5dB, which to the author's knowledge is higher than the VMs published in the literature, and it also achieves a root-mean-square (RMS) gain error and phase error of 0.4dB and 2^0 respectively across the 35-49GHz frequency range. The test chip area is 1.4mmx1.5mm, and the VM core area is 350umx350um.

Keywords: Analog Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: In this paper, an echo-cancellation based hybrid is proposed for simultaneous-bidirectional (SBD) signaling in wireless thru-chip interface (TCI) for 3-D stacked ICs. In case of conventional unidirectional (UD) signaling, separate TCIs for transmitting and receiving data are used. Further with increase in communication distance, the inductor diameter should be increased to maintain the coupling coefficient which increases the quality factor and induces ringing. As a result, the UD signaling limits the data-rate per unit area for a given communication distance.The proposed transceiver incorporates SBD signaling by using a hybrid topology to extract the received signal by cancelling the transmitted signal in the TCI. By this approach the data-rate per unit area has increased by 10% for 1e-9 biterror rate with sampling jitter of 5 ps. The architecture has been implemented using TSMC PDK in 65 nm technology for a communication distance of 25 μm. It achieves a SBD data-rate of 20 Gb/s with an energy-efficiency 1.75 pJ/b.

Keywords: Secure AI Hardware, Hardware Security, AI Digital Hardware, Accelerators, and Circuits
Abstract: Running deep neural networks in the cloud raises privacy concerns. While privacy-preserving machine learning techniques offer promising solutions, they often suffer from long latency due to large polynomials’ replication costs and computational complexity. Diagonal-order matrix multiplication presents a potential avenue for addressing this issue by accelerating ciphertext-to-plaintext operations by efficiently using rotations. However, further performance enhancements are required to make these methods feasible for various platforms. This paper introduces the sparsity tailored for diagonal-order ciphertext-to-plaintext operations with different ratios. By removing several weights parallel to the main diagonal, computational operations, such as rotations, addition, and multiplication, are reduced. Our approach significantly speeds up computations and lowers encrypted inference latency while maintaining model accuracy. Experimental evaluations reveal that with a 1 : 4 diagonal sparsity ratio, the proposed approach achieves a 1.86× speed-up compared to traditional fully connected networks. This method also reduces memory usage to less than 0.343 GB for the entire homomorphic process on the MNIST dataset.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Machine Learning at the Edge, Secure AI Hardware
Abstract: Federated Learning (FL) offers a decentralized Machine Learning (ML) approach that enhances data privacy by allowing local model training without sharing raw data. However, in heterogeneous environments, FL is vulnerable to adversaries, including data poisoning and security breaches, which can compromise the integrity of learning process. The proposed research focuses on addressing heterogeneity and security challenges against adversities in FL through a security-driven framework. The key contribution of this work is to address the heterogeneity in FL by proposing a Hybrid Federated-Centralized Learning (HFCL) and then develop a privacy-preserving HFCL model that is secure from threats. Firstly, a hybrid learning model is presented in which both Centralized ML and FL participate in training. After that, an adversarial threat is attempted on HFCL using the diverse datasets and implemented Differential Privacy (DP) to counteract adversarial threats. The experimental results show that the proposed framework effectively secures models against adversarial threats, achieving 99.15% accuracy on MNIST and 68.4% on CIFAR-10 under privacy constraints. The findings demonstrate that integrating DP-based defenses in a heterogeneous FL environment significantly enhances FL security, ensuring high model accuracy while mitigating adversarial entities.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Neural Learning Circuits & Systems, Machine Learning at the Edge
Abstract: Speculative backpropagation has emerged as a promising technique to accelerate the training of neural networks by overlapping the forward and backward passes. Leveraging speculative weight updates when error gradients fall within a specific threshold reduces training time without substantially compromising accuracy. In this work, we implement speculative backpropagation on the MNIST dataset using OpenMP as the parallel programming platform. OpenMP’s multi-threading capabilities enable simultaneous execution of forward and speculative backpropagation steps, significantly improving training speed. The application is planned for synthesis on a state-of-the-art FPGA to demonstrate its potential for hardware acceleration.

Our CPU-based experimental results demonstrate that speculative backpropagation achieves a maximum speedup of 24% in execution time when using a threshold of 0.25, and accuracy remaining within 3-4% of the baseline across various epochs. Additionally, when comparing individual step execution time, speculative backpropagation yields a maximum speedup of 35% over the baseline, demonstrating the effectiveness of overlapping forward and backward passes.

Keywords: AI-IoT Systems and Applications, Wearable Smart Sensor Systems, Other Areas in Biomedical Circuits and Systems
Abstract: A wireless sensor node (WSN) system offers an effective solution for monitoring pig activity by sensing motion and transmitting data wirelessly. However, continuous sampling and transmission of raw sensor data leads to significant power consumption, requiring frequent battery maintenance. This paper presents an edge computing approach that addresses this challenge by integrating a trained Random Forest Classifier (RFC) into the WSN. While the RFC itself does not directly reduce power consumption, it enables adaptive control of the sampling rate based on predicted animal behaviors, thereby lowering energy usage. Furthermore, replacing raw data transmission with RFC-based behavior predictions significantly reduces the communication load. The proposed system classifies key activities—eating, drinking, lying, standing, and walking—with an F1-score of 93%. Compared to conventional WSNs transmitting raw data at a fixed 10 Hz rate, the edge-enhanced system achieves a 25% reduction in power consumption.

Keywords: Machine Learning at the Edge, AI-IoT Systems and Applications
Abstract: Flooding poses significant risks to both infrastructure and human life. While remote flood monitoring systems have advanced with the rise of IoT devices, traditional hydrological models and many machine learning approaches for flood prediction remain computationally intensive, hindering deployment on resource-constrained hardware. This study presents a lightweight multilayer perceptron (MLP) model optimized for execution on a microcontroller, enabling real-time flood prediction directly on the low-power device. Through automated hyperparameter tuning and full integer quantization, the model achieves an 86.5% reduction in size with minimal loss in predictive accuracy. When deployed on a Raspberry Pi Pico, the quantized MLP demonstrates performance comparable to the full-precision model, achieving Nash-Sutcliffe Efficiency (NSE) and Coefficient of Determination values greater than 0.9 and MPAE of 3.4%. This edge-based solution provides a viable approach to decentralized flood monitoring.

Keywords: Machine Learning at the Edge
Abstract: Advancements in data acquisition of space-grade sensor technology are rapidly outpacing both the downlink bandwidth and onboard storage capacity of spacecraft. At the same time, radiation-tolerant hardware continues to lag behind state-of-the-art terrestrial systems, limiting the feasibility of deploying modern data processing techniques in space environments. As a result, there is a growing need to develop methodologies that enable efficient execution of advanced data processing models on radiation-hardened hardware. This paper presents and evaluates the performance of an extremely quantized image processing architecture trained to detect surface novelties on Mars surface. Through binarization, the model size was reduced to just 3% of the original baseline, eliminating all floating-point multiplications while incurring only a 1.06% reduction in test accuracy.

Keywords: Machine Learning at the Edge, Artificial Intelligence for Complex Networks and Nonlinear Systems, AI-IoT Systems and Applications
Abstract: The convolutional network is the preferred option for handling large input sizes and is commonly used in neural networks for most applications. In this experiment we demonstrate the performance of a modified convolutional neural networks (CNN) using an exponent based weight. The Exponential Convolutional Neural Network (ECNN) was tested on bacteria classification, with different model deployed on edge devices such as a Raspberry Pi and Esp32. Additionally we created a model with 3-output that can detect a specific bacteria like E. coli, aiding environmental engineers in improving efficiency. As a result, our 4-layer standard CNN model was able to achieve an accuracy of 85% for 30 bacteria strains and this 4-layer model was successfully deployed to an edge device (the Raspberry Pi 5), with model quantization using TensorFlow Lite. ECNN is having an accuracy of 68% on test set and 89% accuracy training set. This study shows the potential of deploying a CNN for bacterial detection on edge devices. Future work will be focused on improving model generalization, reducing overfitting, and improving real-time inference performance to create a more reliable and efficient system for the environment and water quality monitoring.