Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a 140dB CMRR rail-to-rail input/output low-voltage precision differential amplifier, composed of a high-CMRR chopper-stabilized precision operational amplifier and a precision resistor trimming network. For the chopper-stabilized op-amp, a CMRR enhanced input stage is proposed, utilizing a common-mode voltage sampling charge pump (VCMCP) circuit to ensure constant input chopper switch on-resistance and input pair operation across the entire common-mode voltage (VCM) range. Rail-to-rail input is achieved using PMOS pairs, avoiding offset voltage shifts caused by NMOS and PMOS pair switching, thereby enhancing CMRR. For the precision resistor trimming network, the E-TRIM technique is employed to trim resistor mismatches, and a VCMCP provides control voltage for the trimming logic. Compared to traditional transmission gate structures, the on-resistance of the trimming switches remains stable with supply and reference voltages, ensuring the precision of the resistor matching network. Finally, using a 0.18µm process, a 140dB CMRR rail-to-rail input/output precision differential amplifier is designed and fabricated. The amplifier operates from 1.8V to 5.5V, consumes 450µA, has a maximum offset voltage of 2.5µV, and a noise power spectral density of 10nV/sqrt(Hz). Simulation and test results demonstrate a superior CMRR of 140dB.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Human/brain-Machine Interfaces
Abstract: Bootstrapped switches have been used in samplers to suppress harmonic distortions due to the input-dependent on-resistance and charge injection of the sampling switches. The principle is to create an input-related voltage boost across the switch. However, such switches are commonly under the stress of dielectric breakdown because of over-the-supply-rail boosted voltage. Prior art relieves such stress with increased design complexity by using more transistors. This work uses only five transistors and two capacitors (5T2C) to create a compact and reliable bootstrapped switch that avoids any time-dependent dielectric breakdown (TDDB). The switch design demonstrates a similar linearity with less power for oversampled applications, compared to conventional ones. It becomes the most compact when it comes to a fixed voltage clock bootstrapping.

Keywords: Other Analog/RF Circuits and Systems, Physical Design, Test, Verifications, Other Power Circuits and Systems
Abstract: The RC-based power-rail electrostatic discharge (ESD) clamp has been widely used to enhance ESD robustness of the integrat-ed circuits (ICs). However, the power-rail ESD clamp circuit may be falsely triggered under fast power-on operation. In ad-dition, it is inevitable to be drawn with large layout area for achieving sufficient RC time constant. In this work, a new pow-er-rail ESD clamp circuit with a hybrid detection mechanism was proposed and successfully verified in a 0.18-µm 1.8-V CMOS technology. In the proposed power clamp, the standby leakage current under a 1.8-V voltage is only 9.7 nA, and the HBM ESD level of 5.5 kV is achieved by a MESD of 400 µm. With better area efficiency and high immunity to false triggering issue under fast power-on operation, the new proposed power-rail ESD clamp circuit is an excellent solution for on-chip ESD protection in modern CMOS IC products.

Keywords: Analog Circuits and Systems, Regulators, References and Reliability Methods
Abstract: This paper presents a voltage reference design using MOSFETs in weak inversion with translinear temperature compensation technique to minimize area and power consumption in traditional voltage references while achieving a low temperature coefficient (TC). The translinear compensation technique reduces the nonlinearity inherent in the gate-to-source voltage (Vgs) of weak inversion transistors. Simulations indicate that the proposed reference achieves a TC of 2.2 ppm/℃ from -40℃ to 140℃, power supply ripple rejection of -45.5 dB, power consumption of 3.65uW and takes up 0.03mm² area. Monte Carlo analysis with 200 samples yields a mean TC of 3.75 ppm/℃ with a standard deviation of 0.5ppm/℃ when trimmed at 27℃ and 105℃.

Keywords: Analog Circuits and Systems, Regulators, References and Reliability Methods, Wearable Smart Sensor Systems
Abstract: Recent advancements in low-power and low-voltage integrated circuits have spurred significant research interest, particularly for applications with demanding supply conditions. This work presents a single-branch voltage reference achieving exceptional immunity to supply voltage variations. Leveraging a ΔVGS-based approach, the design utilizes transistors with different channel lengths to exploit geometry-dependent threshold voltage differences, enabling effective temperature compensation. Additionally, a multi-self-cascoded technique enhances immunity to supply voltage variations. Post-layout simulations of a 0.18-μm CMOS design, operating with supply voltage as low as 0.45 V, demonstrate a line sensitivity of 2.73 ppm/V and a temperature coefficient of 20.1 ppm/◦C, with power consumption below 200 pW. The proposed architecture is shown to be a robust solution for implementing precise, low-voltage and low-power voltage references.

Keywords: Analog Circuits and Systems
Abstract: This paper introduces a compact curvature-compensated voltage reference design using subthreshold MOS devices and no amplifiers. The proposed approach generates an accurate temperature-stable reference by adding linear and curvature correction voltages to the MOS subthreshold gate source voltage, VGS . The proposed circuit was designed in TSMC 180nm and verified over a wide temperature range from −40◦C to 125◦C. Monte Carlo simulations across process and local random variations show that, the proposed circuit achieves a worst case temperature coefficient (TC) less than 3.8ppm/◦C with a mean and spread of 3.21ppm/◦C and 0.24ppm/◦C respectively, after a standard 3 temperature trim. The post-trim TC further improves with additional temperature trims, achieving a mean value of 2.28ppm/◦C and a spread of 0.14ppm/◦C. The proposed voltage reference occupies 0.008mm2 area.

Keywords: Sensor Interface Circuits and Microsystems, Analog Circuits and Systems
Abstract: This paper presents a light-to-frequency converter composed of a novel integrated analog-front-end circuit including a photodiode to measure changes of light intensity impinging on it. The fabricated ASIC powered at 1.8 V was designed at transistor level in TSMC 0.18 µm standard CMOS technology for low-voltage low-power operation to be employed in wearable and implantable optical sensors in industry, agriculture and biomedicine. Light intensity variations are measured through the frequency modulation of a square waveform generated by the designed circuit whose quasi-digital output can be evaluated by digital frequency meters so avoiding the use of transimpedance amplifiers and analog-to-digital converters. The presented work reports on the electrical characterization of both the photodiode and the analog-front-end circuit for different current gains. Moreover, the optical characteristics of the light-to-frequency converter were provided using a laser in continuous and pulsed operating conditions. By setting the highest current gain, the system sensitivity was 859.1 kHz/uW with a resolution of 11.6 pW and a maximum power consumption of 104 uW. The comparison of the experimental results with those of similar integrated solutions reported in literature demonstrates that the proposed system uses a very small area achieving the best values of sensitivity, resolution, and power consumption.

Keywords: Analog Circuits and Systems, Other Analog/RF Circuits and Systems, Sensor Interface Circuits and Microsystems
Abstract: This paper presents a low-power innovative frequency-to-voltage converter (FVC) with tunable frequency range and sensitivity for sensor readout applications. The proposed FVC is implemented in a 1P8M 65-nm standard CMOS and does not use a reference clock; it takes advantage of the capacitance charging/discharging and charge redistribution to enable operation across a wide frequency ranging from hundreds of KHz to several MHz. The measured results show a sensitivity ~ 6000 mV/MHz and linearity better than 0.2% with a flexible tuning range from 5% to 10%.

Keywords: Other Sensory Circuits and Systems, Physical and Chemical Smart Sensing Systems, Analog Circuits and Systems
Abstract: This paper presents a low-power application-specific integrated circuit (ASIC) in CMOS technology for impedance sensing. The system consists of an incremental ∆–Σ modulator and a finite-state machine (FSM) with a bridge transducer and a variable resistance analog front end module. All modules were designed in commercial 0.18 μm CMOS technology. The ADC provides a peak positive and peak negative DNL of +0.22 LSB and -0.2 LSB, respectively, while the peak positive and peak negative INL are +0.71 LSB and -0.89 LSB, respectively. The Signal-to-Noise Ratio of the ADC is calculated to be 91.33 dB.

Keywords: Technologies for Smart Sensors, Analog Circuits and Systems, Internet of Things (IoT) Theory and Systems
Abstract: This paper presents a calibration-free temperature sensor based on thermal diffusivity, designed for high-accuracy Internet of Things (IoT) smart sensing. Operating over a wide temperature range of 0°C to 100°C, the sensor achieves a temperature accuracy of ±0.8°C and a resolution of 0.01°C. Unlike conventional sensors that require extensive calibration, this design uses silicon’s thermal diffusivity, enabling robust and calibration-free temperature measurements. The sensing mechanism relies on oscillation frequency variations, where temperature is determined by counting oscillation cycles over a defined period. The proposed architecture is compact, energy efficient, and highly reliable, making it well-suited for massive deployment IoT applications, particularly in low-power, short-range sensor nodes.

Keywords: Technologies for Smart Sensors
Abstract: This paper presents a wireless low-power gait sensor for the extraction of gait patterns. The gait sensor senses the pressures of the ball and heel areas of a foot at the rate of 10 samples per second and transmits the data via Bluetooth Low Energy (BLE). To save power, the main processor wakes up every 1.0725 seconds, transmits the accumulated data, and then goes back to standby mode. The gait sensor attached to the shin of a person collected data for three different gait patterns, standing, walking, and running. Measurement results show that the gait sensor dissipates 24.7 μW in the standby mode and 59.1 μW during transmission, and the average power dissipation is 24.9 μW.

Keywords: Wearable Smart Sensor Systems, Point-of-Care Biomedical Diagnostics
Abstract: This paper describes a wearable A-mode ultrasound device designed to track human scapular movements during rehabilitation following reverse shoulder replacement surgery. The proposed device uses a 5×5 array of transducer PCBs to measure variations in bone depth at different locations in the scapular region over time and generate a pattern of scapular movements. Each transducer PCB contains an individual transmitter and receiver (transceiver) and functions as a standalone A-mode ultrasound device. This enables a highly reconfigurable system, enhancing its flexibility for monitoring the motion of different body parts and potentially enabling its use in other applications. The bone depth measurements utilize matched filtering by correlating the received echo signals with a template signal derived from a Manchester-encoded pseudo-random transmit pulse. The resulting pulse compression optimizes the signal-to-noise ratio (SNR) and depth resolution, allowing for the accurate detection and differentiation of small bone targets. Experimental results on an ultrasound phantom confirm system functionality.

Keywords: Other Areas in Biomedical Circuits and Systems, Analog Circuits and Systems, Integrated Biomedical Systems
Abstract: Microbubble cavitation may contribute to blastinduced traumatic brain injuries. While traditional benchtop systems for detecting and localizing cavitation sources offer high precision, their large size and high cost make them impractical for use in field applications. This paper introduces a wearable system for continuous detection and 3D-localization of cavitation sources by measuring the time difference of arrival (TDOA) of ultrasound signals captured by four transducers. The system consists of four identical analog frontend channels, each with measured tunable gain of up to 39.3 dB within a bandwidth of ~ 17.9 kHz to 1.1 MHz. It also includes a microcontroller and wireless module that can sample signals at ~ 8.3 Mega sample per second (MSps) with 8-bit resolution. The proposed system processes data onboard for real time detection of cavitation onset and efficiently manages data by storing and selectively transmitting only relevant data through a robust local wireless network to a PC for detailed analysis and accurate identification of cavitation events and their source locations. In measurements, the system achieved a maximum TDOA detection error of 288 ns across four channels using 20 mV (peak-peak), 500 kHz ringing signals as input. Our initial 2D localization experiments using three piezoelectric transducers demonstrated an accuracy of 1.95±0.66 mm for sources located within a 50 mm radius from the transducers’ geometric center.

Keywords: Implantable/injectable Systems, Integrated Biomedical Systems, Human/brain-Machine Interfaces
Abstract: Abstract—This paper presents a miniaturized, energy-efficient 2×2-channel neural recording front-end IC for high-density neural signal acquisition. Each channel features a bandwidth- and gain-tunable Analog Front-End (AFE) and a 10-bit Successive-Approximation Register (SAR) ADC. The AFE employs a capacitive feedback network with voltage-controlled pseudo-resistors and digitally controlled capacitors, enabling tunable bandwidth (0.1-5 kHz) and gain (40-50 dB). The SAR ADC utilizes a bootstrapped switch and monotonic switching scheme, reducing switching energy by 81% while achieving an SNDR of 57.8 dB and an ENOB of 9.3 bits. The IC integrates a clock recovery unit that extracts a 1.1 MHz square wave with 1 μW of power consumption, eliminating the need for an on-chip oscillator. The entire design is based on TSMC 180 nm CMOS technology, occupying a total area of 2.2 × 2.3mm>².

Keywords: Hardware-Software Co-Design, Physical and Chemical Smart Sensing Systems, Communications Systems and Control
Abstract: This paper describes design and fabrication of real-time smart bandage network by the utilization of Bluetooth Low Energy 5 (BLE5) technology. We have designed and fabricated a system where smart bandages are employed to continuously monitor wounds, transmitting the collected data to a central unit via BLE5. Each smart bandage is equipped with an ultra-low-power (ULP) dual core microcontroller (MCU) connected to sensing nodes capable of measuring temperature, humidity, pressure, and gas resistance. The measured sensor data is relayed to the central unit for visualization, storage, and further analysis. The paper details the algorithms developed for both the smart bandages and the central unit, emphasizing their efficiency, scalability, resilience, and reliability. This research advances the development of affordable healthcare systems by enhancing the capabilities of real-time wound monitoring.

Keywords: Other Areas in Biomedical Circuits and Systems, Implantable/injectable Systems, Integrated Biomedical Systems
Abstract: Hydrocephalus, caused by impaired cerebrospinal fluid (CSF) circulation, leads to elevated intracranial pressure (ICP). Traditional shunts regulate CSF drainage but often fail, so we fabricated a sub-millimeter PDMS duckbill valve and analyzed it with a circuit model. A benchtop sub-model was tuned to the valve’s measured pressure–flow (P–Q) curve, and the resulting parameters were ported into a CSF-dynamics circuit model. Simulations of both mild (17.5 mmHg) and severe (25 mmHg) hydrocephalus show that a dual-0.8 mm valve cuts ICP to around 11 mmHg in 30 s, outperforming single-valve setups (12–14.5 mmHg) and the no-valve baseline. Integrating circuit simulation with experimental data gives a fast, quantitative screen for valve geometry and provides a path toward data-driven optimization of valve configurations for hydrocephalus.

Keywords: Implantable/injectable Systems, Human/brain-Machine Interfaces, Integrated Biomedical Systems
Abstract: High-density implantable integrated neural interfaces are at the forefront of treating neural disorders, offering potential for medical advancements. Effective neural recording relies heavily on the noise performance and spatial coverage of the neural interface. The noise performance determines the recording accuracy, while spatial coverage dictates the number of simultaneous recording sites. Typically, increasing spatial coverage and reducing noise presents a trade-off. This paper explores the balance between spatial resolution and noise performance in two types of neural implants: central nervous system (CNS) and peripheral nervous system (PNS) applications. CNS recordings require high spatial resolution to accurately capture neuronal activity, while PNS recordings prioritize low noise levels due to the micro-volt range of neural signals. Despite significant advancements in high-density neural interfaces, current technology still falls short of the spatial density required for neuroscience research. This paper presents a comprehensive strategy for optimizing multiplexed channel structures by addressing factors such as area, signal-to-noise ratio, bandwidth, and noise limitations. Optimizing the number of electrodes per channel can enhance the performance of neural recording systems. This paper analyzes the design trade-offs and provides insights into the number of electrodes per channel for neural interfaces.

Keywords: Implantable/injectable Systems, Analog Circuits and Systems
Abstract: Implantable Medical Devices (IMD) have been around for few decades and they form a big piece of the new group of therapeutic agents known as the Electroceuticals. In the spectrum of healing, IMDs are positioned between drugs and surgery and have increasingly become acceptable as well as available, thereby providing patients life-saving therapies like cardiac pacing to well-being monitoring like glucose tracking. One of the groundbreaking applications of IMDs has been neurostimulation based Deep Brain Stimulation (DBS) and Spinal Cord Stimulation (SCS), where not only ailments like Epilepsy and Parkinson’s Disease have been successfully addressed but effective pain management has been achieved. The advancement in treatment based on neurostimulation needs a closed loop system where the patient needs are addressed quickly. The impediment in that pursuit has been the existence of artifacts in the neural sensing path. This review presents an overview of challenges presented by artifacts and the state-of-the-art in circuit-based artifact cancellation techniques applied to achieve concurrent neural sensing and stimulation.

Keywords: Image, Video and Multi-Dimensional Signal Processing, Other Signal and Image Processing, Deep Learning for Multimedia
Abstract: Medical image segmentation is crucial for computer-aided diagnosis, yet traditional deep learning models often fail to generalize across different domains due to variations in acquisition settings. We propose a source-free, integrated novel continual learning scheme for domain-incremental medical image segmentation. Our scheme consists of three different steps that use U-Net to train on a source domain in the first step, evaluate zero-shot performance on a target domain in the second step, and re-evaluate on the source to assess forgetting in the third step. Without accessing prior data during adaptation, our method remains privacy-preserving and scalable. Experiments show high performance on the source domain, competitive results on the target domain, and minimal forgetting. The performances are measured in terms of dice score, Hausdorff distance (HD), and average symmetric surface distance (ASSD). Compared to the state-of-the-art, our approach balances generalization and retention, showing robustness under domain shifts. Our proposed work establishes a reproducible and clinically practical benchmark using continual learning in segmentation.

Keywords: Signal Processing Theory and Methods
Abstract: Polynomial modular multiplication is an important operation used in post-quantum cryptography and homomorphic encryption, which are based on ring learning with errors (RLWE) problems. For long polynomial lengths, this operation can be efficiently computed using number theoretic transform (NTT) and inverse NTT (INTT). In particular, negative wrapped convolution (NWC) has been proposed to compute this operation where zero padding is eliminated. Low-complexity structures for NTT (LC-NTT) and INTT (LC-INTT) have been derived in prior work by using a divide-and-conquer approach. This paper presents an alternate derivation of the LC-NTT and LC-INTT structures from traditional NTT and INTT structures. Specifically, we show that using twiddle factor pushing (pulling) from left to right (right to left), we can derive the prior LC-NTT (LC-INTT) structures. We present systematic algorithms for twiddle factor pushing and pulling to derive the equivalent architectures. The alternate approach may provide opportunities for optimizing hardware implementations of polynomial modular multiplication.

Keywords: Neural Learning System Algorithms and Applications, Machine Learning at the Edge, Signal Processing Theory and Methods
Abstract: The FFT has taken physics-informed neural network (PINN) for advanced simulations by storm. FFT based Fourier Neural Operators (FNOs) have led to massive reductions in compute requirements for partial differential equation (PDE) based classical physics simulations with extensive applications in climate modeling, turbulent flow modeling, and magnetohydronamics, as well as other branches of classical physics. The use of FFT based FNO-PINN models has reduced the complexity of massively complicated physics simulations from mathcal{O}(N^2) to mathcal{O}(Nlog N). In this work, we propose replacing FFTs with sparse factorized approximate DFT algorithms, which lead to the novel concept of approximate FNOs, which further reduce the compute requirements by a further log N factor resulting in linear complexity mathcal{O}(N) algorithms for PINNs. Early work from open source FNO examples shows promising results for both Darcy flow and Navier-Stokes PDE problems.

Keywords: Signal Processing Theory and Methods, Image, Video and Multi-Dimensional Signal Processing, Other Signal and Image Processing
Abstract: This paper explores a trajectory-based local navi- gator for mobile robots in which system identification is used to identify a kinodynamic model that generates trajectories capturing vehicle drivability constraints. A physics-based differential-drive model produces the ground-truth dataset which in combination with velocity command sequences inform an Auto- Regressive eXogenous input (ARX) system framework. Experi- mental evaluations are conducted across diverse driving scenarios and vehicle loading conditions, incorporating both training and validation datasets. The identified models demonstrate strong predictive capability, with the resulting trajectories closely match- ing ground-truth paths and validating the effectiveness of the proposed approach.

Keywords: Image, Video and Multi-Dimensional Signal Processing, Other Signal and Image Processing
Abstract: This work introduces a multi-stage computer vision algorithm that detects and tracks road lanes presented in a video format. Rural, poorly-marked lanes are of particular interest as they present special challenges for lane extraction. A novel combination of classical image processing techniques including illumination normalization, morphological processing and geometric warping are cooperatively applied. This paper presents the various stages of the image processing pipeline, applying algorithms to an extended rural-road video. Excellent results are demonstrated indicating that a reliable algorithm that can adapt to diverse driving scenes and conditions is presented

Keywords: Other Signal and Image Processing, Analog, Digital and Mixed Signal Processing, Signal Processing Theory and Methods
Abstract: Biomedical signal processing is essential for analyzing EEG and ECG signals, which are often non-stationary and require time-frequency analysis for effective classification. In this work, Short-Time Fourier Transform (STFT) integrated with Continuous Wavelet Transform (CWT) is proposed to enhance feature extraction and classification accuracy. Discrete Wavelet Transform (DWT) is employed for signal denoising and converting 1D signals into 2D spectrograms and scalograms, enabling CNN-based deep learning for improved classification. The experiment results indicate that wavelet-based multi-resolution analysis significantly enhances signal classification accuracy, benefiting disease detection and human activity recognition.

Keywords: Integrated Biomedical Systems, AI-IoT Systems and Applications, Machine Learning at the Edge
Abstract: Pulse oximetry is a standard method for noninvasive clinical monitoring of peripheral oxygen saturation (SpO2), a key vital sign, yet studies highlight its reduced accuracy in individuals with darker skin pigmentation, often resulting in occult hypoxemia. This discrepancy arises from calibration biases and the optical effects of elevated melanin levels, which interfere with light transmission and absorption. To address this disparity, we propose a lightweight, machine learning-based correction model that estimates arterial oxygen saturation from SpO2 readings by incorporating demographic and skin pigmentation metrics. Leveraging the OpenOximetry dataset and deploying compact neural networks, we trained and optimized a model suitable for real-time operation on resource-constrained edge hardware. The model was quantized using TensorFlow Lite to minimize memory and computation requirements. Deployment and testing on a Raspberry Pi 5 confirmed feasibility, with the quantized model achieving an RMSE of 2.103% and R2 of 0.947 while requiring 43.5 KB of RAM and 122 ms inference time. Our approach demonstrates a viable path to bias-aware, accurate oxygen monitoring by enabling demographically informed SpO2 correction on edge devices.

Keywords: Biomedical Signal/Image Processing, Integrated Biomedical Systems, Other Areas in Biomedical Circuits and Systems
Abstract: Transcutaneous blood gas monitoring is a noninvasive technique to assess oxygen levels in medical applications. The luminescence-based, transcutaneous blood oxygen monitor is a novel, nonthermal device designed to track the blood oxygen level noninvasively. This paper investigates the temperature sensitivity of the novel device and proposes a low-power calibration algorithm to compensate for temperature dependence and improve the accuracy of the sensor's reading. Temperature fluctuation impacts the emission properties of the sensing film, leading to fluctuation in the sensor readings. Experiments conducted at 3 constant temperatures (22°C, 30°C, and 40°C) demonstrate that the novel device has the sensitivity of -0.14 (mu)s (/)°C to temperature. Furthermore, a temperature sweep analysis (22°C - 42°C) reveals that the lifetime value has a maximum deviation of 17% at 42 °C from the baseline value at 22°C. The proposed temperature compensation technique, implemented on the microcontroller on board, alleviates the deviation down to 1%.

Keywords: Integrated Biomedical Systems, Physical Design, Test, Verifications, Wearable Smart Sensor Systems
Abstract: Accurate oxygen measurement in neonates is critical for monitoring respiratory function, preventing hypoxia and hyperoxia, and supporting optimal developmental outcomes, including healthy brain development, cognitive function, and overall growth. A transcutaneous oxygen monitor is a noninvasive device that measures the partial pressure of oxygen diffusing through the skin in humans. We introduce a device that employs a luminescent film sensitive to oxygen variations to measure the decay of the luminescent signal. The luminescence decay time is inversely proportional to oxygen levels, meaning higher oxygen levels result in a shorter decay time. Despite recent advancements aimed at enhancing measurement accuracy, existing devices remain relatively large for infants and lack a reliable method for adhering to the delicate skin of newborns. In this study, we present two key advancements: a compact transcutaneous oxygen monitor with a diameter of 27 mm, and a soft silicone encapsulation featuring a skin-safe adhesive interface. Together, these innovations enhance the wearability, comfort, and safety of the device, making it well-suited for use in infants. We conducted tests on a human subject to detect oxygen variations by applying occlusions that restricted blood flow, thereby reducing oxygen delivery to the targeted body area. The device can successfully identify changes in oxygen levels. Initial tests suggest that using a softer silicone improves adhesion to the skin.

Keywords: AI-IoT Systems and Applications, Biomedical Signal/Image Processing
Abstract: The growing use of wearable technology for health and activity tracking requires efficient machine learning (ML) models that can handle real-time data on low-power devices. This paper investigates the potential efficiency improvements that Hyperdimensional Computing (HDC) offers compared to more established, conventional ML models. These conventional models include SVM, MLP, and Random Forest models, all of which we implement within an Android WearOS application for comparison. In such resource and power-constrained environments, even modest improvements in power efficiency can significantly impact the feasibility of real-time model deployment, particularly for applications such as activity trackers or health monitors, where fast execution is critical. Accordingly, this study evaluates key metrics including model accuracy, CPU usage, memory usage, and especially power and battery usage. The findings of this study indicate that HDC not only achieves competitive accuracy but also offers substantially higher computational efficiency compared to traditional models.

Keywords: Emerging Memory and Memristor, Neuromorphic Circuits and Systems
Abstract: The growing energy demands of information and communication technologies, driven by data-intensive computing and the von Neumann bottleneck, underscore the need for energy-efficient alternatives. Resistive random-access memory (RRAM) devices have emerged as promising candidates for beyond von Neumann computing paradigms, such as neuromorphic computing, offering voltage-history-dependent switching that mimics synaptic and neural behaviors. Atomic-scale mechanisms, such as defect-driven filament formation and ionic transport, govern these switching processes. In this work, we present a comprehensive characterization of Tantalum Oxide based RRAM devices featuring both oxygen-rich and oxygen-deficient switching layers. We analyze the dominant conduction mechanisms underpinning resistive switching and systematically evaluate how oxygen stoichiometry influences device behavior. Leveraging a bottom-up design methodology, we link material composition to electrical performance metrics—such as endurance, cycle-to-cycle variability, and multilevel resistance states—providing actionable guidelines for optimizing RRAM architectures for energy-efficient memory and computing applications.

Keywords: Analog Circuits and Systems, Physical Design, Test, Verifications
Abstract: Direct time-of-flight (ToF) light detection and ranging (LiDAR) is a powerful imaging technique for depth sensing and 3D mapping. Single-photon avalanche diodes (SPADs) serve as high-sensitivity detectors, enabling precise photon-based measurements. Power consumption is a critical factor in Single-Photon Avalanche Diode (SPAD) readout, especially for pulsed LiDAR applications. This work explores the power trade-offs in the readout chain, focusing on the quench and reset (QAR) block. We model the SPAD and use circuit-level simulations to evaluate the power-performance characteristics of the QAR. We found that the active quench and reset (AQAR) saves more than 75 percent of power compared to a passive quench circuit. The insights from our study serve to guide design choices for optimizing SPAD-based ToF LiDAR systems.

Keywords: Heterogeneous Integration, AI-IoT Systems and Applications, Sensor Fusion
Abstract: Advanced heterogeneous systems increasingly rely on high-density packaging technologies such as 2.5D and 3D integration, which utilize vertical interconnects---including through-substrate vias (TSVs), micro-vias, and copper pillars---along with redistribution layers (RDLs) and solder bumps. Existing finite element method (FEM) based tools are computationally intensive, while traditional analytical models fail to capture high-frequency behavior above 20 GHz. To address this gap, a lightweight circuit-level simulation framework is developed to accurately model high-frequency effects---including coupling and skin effects---up to 100 GHz with less than 5% deviation from FEM tools and up to 30X speedup. Using this framework, signal transmission efficiency is evaluated across three interconnect architectures: (i) two-dimensional (2D), integrated on printed circuit board (PCB), (ii) heterogeneously integrated on an interposer (2.5D), and (iii) hybrid, interposer and three-dimensional (2.5D/3D). Based on the results, the 2D structure retains only 10% of the transmitted power, whereas the 2.5D and 2.5D/3D configurations retain 80% and 90%, respectively. These findings highlight the critical importance of interconnect architecture in mmWave systems and validate the proposed framework as an effective tool for design exploration of advanced sensor array packaging.

Keywords: Neural Learning System Algorithms and Applications, RF Front-End Circuits, Artificial Intelligence for Complex Networks and Nonlinear Systems
Abstract: Modeling radio-frequency (RF) circuits at the transistor level remains challenging due to their nonlinear behavior, layout sensitivity, and complex topologies. While traditional simulation methods offer accuracy, they are computationally prohibitive for large-scale design exploration and post-layout verification. Recent machine learning (ML) approaches, particularly block-level models, have improved modeling efficiency but often ignore critical topology-dependent effects. This paper reviews emerging AI-assisted techniques for RF circuit modeling, with a focus on graph neural networks (GNNs) as a promising topology-aware solution. We analyze their potential to generalize across architectures, capture layout parasitics, and reduce simulation costs. Limitations such as data requirements, scalability, and generalization to complex RF circuits are discussed. The paper identifies key open challenges and outlines future directions by analyzing the limitations of existing GNN-based analog circuit models and evaluating their extensibility to RF design, highlighting the adaptations needed for frequency-aware, layout-sensitive, and topology-generalizable modeling.

Keywords: Analog Circuits and Systems, Sensor Interface Circuits and Microsystems, Converters, ADC, DAC and others
Abstract: This paper presents a robust Quadrature Bitstream Integration (QuBI-CT Delta Sigma) phasemeter in 40nm LP CMOS that achieves sub-1 degree phase error across the 0 degree-360 degree input range and 0 degree Celsius to 70 degree Celsius temperature range. The phasemeter utilizes a third order CT Delta Sigma modulator and accumulating digital backend to form I and Q components of the input waveform. For improved linearity the CT Delta Sigma modulator utilizes feedforward resistive DACs and a single-bit quantizer. To reduce the effects of flicker noise, chopping in the first amplifier stage is used. Using a 1kHz input tone the modulator achieves a SNDR of 68.9 dB and has an oversampling ratio of 256 and bandwidth of 4kHz. The ADC consumes 112 uW and the Quadrature Bitstream Integration consumes 200 nW. The prototype design consumes 27.7 nJ/reading and occupies only 0.094mm².

Keywords: Analog, Digital and Mixed Signal Processing, RF Front-End Circuits, Converters, ADC, DAC and others
Abstract: Testing array processing algorithms requires realistic data that captures both hardware non-idealities and environmental complexities, but collecting comprehensive experimental datasets is often impractical. We present an open-source end-to-end simulator that addresses this challenge by providing a modular, GPU-accelerated framework for evaluating array processing algorithms under realistic conditions. Our simulator integrates high-fidelity models of the entire processing chain, from waveform generation through downstream tasks. Key innovations include a complete PyTorch-based implementation that enables efficient simulation of dynamic wireless channels, RF frontend non-idealities, digitization artifacts, and algorithms for beamforming and imaging. Simulated results on realistic scenarios demonstrate the performance of both classical and modern array processing algorithms with the effect of various detrimental effects. The simulator provides researchers with a powerful tool for prototyping and evaluating array processing algorithms for hardware deployment.

Keywords: Implantable/injectable Systems, Integrated Biomedical Systems, Other Areas in Biomedical Circuits and Systems
Abstract: This paper presents an efficient closed-loop control system for implanted microscale vagus nerve stimulators (VNS) that can regulate heart-rate variability (HRV) using a technique inspired by natural homeostasis mechanisms. The sensing of HRV is performed through a PPG sensor patch on top of the carotid artery. In-sensor analytics in the patch calculates RMS successive RR interval differences to quantify HRV, which then activates the microscale VNS for automatic regulation.

Keywords: Wearable Smart Sensor Systems, Signal Processing Theory and Methods
Abstract: This paper presents a computationally efficient Discrete Wavelet Transform (DWT) compression algorithm designed for implementation in resource-constrained microcontrollers (MCU) of wearable devices for electrophysiological (ExG) processing. With such a limited computational resource, we introduce two major strategies to improve the proposed algorithm’s computational efficiency. First, given that ExG signals usually exhibit distinct specific patterns, the DWT for them can be simplified by focusing on certain wavelet levels. This excludes redundant convolution operations and resulting wavelet coefficients, reducing the computation load. Second, the algorithm employs a splitting strategy that distributes the DWT computation load across the intervals of other MCUs’ tasks, such as data sampling, to reduce the peak computation time. To verify the performance of the proposed computationally efficient algorithm, we implemented it in the MCU (nRF52832) using the MIT-BIH ECG dataset as input. Extensive evaluations demonstrate that the proposed DWT algorithm achieves a 3.62× compression ratio (CR) with a percentage root-mean-square difference (PRD) of 3.1%. Moreover, our algorithm reduces total computation time by 2.9× and peak computation time by 20.9×.

Keywords: Hardware Security, Wearable Smart Sensor Systems, Implantable/injectable Systems
Abstract: In this paper, we present Pasteables, a flexible platform for secure health monitoring through a network of on-body, stick-and-peel, intelligent sensing devices. These devices are equipped with appropriate sensors and integrate compute, storage, and communication capabilities, along with embedded intelligence to extract meaningful insights into health conditions. Despite their advantages, these devices, similar to wearables and implants, are susceptible to a range of confidentiality and integrity threats. We identify the key security and privacy challenges associated with these systems and propose low-cost, effective countermeasures. Additionally, we outline future research directions in the security of such devices.

Keywords: Communications Circuits, Theory and Applications, Analog Circuits and Systems, Technologies for Smart Sensors
Abstract: This paper comprehensively reviews the evolution of Electro-Quasistatic (EQS) Human Body Communication (HBC) circuit models for wireless on-body communication and powering. As the Internet of Bodies (IoB) rapidly advances, driven by innovations in communication, security, and computing, HBC has emerged as a key technology offering high-speed, low-power data transmission through the body itself. This approach promises reliable communication and the potential for perpetual nodes via ultra-low-power operation and energy harvesting. Building on the foundational IoB vision established in prior work, we consolidate key insights from recent developments in HBC circuit modeling, with an emphasis on understanding the human body as a communication and power transfer medium. The review covers both capacitive and galvanic EQS-HBC models, analyzing the role of parasitic capacitance and the transition conditions between unsymmetrical galvanic and capacitive modes. We also discuss future opportunities and challenges in resonant-HBC, which enables higher data rates. This work provides a structured foundation for advancing low-power, secure, and scalable body-centric communication systems.

Keywords: Wearable Smart Sensor Systems, Organic and Flexible Circuits and Systems, Other Areas in Biomedical Circuits and Systems
Abstract: This paper introduces an innovative platform for head motion tracking using soft gels of eutectic solvents, namely eutectogels. Eutectogels are flexible, conformal, and inconspicuous for on-skin strain sensing applications. The experimental results show that the eutectogel strain sensor exhibits a gauge factor of approximately 1.34 at 1 kHz. A multiplexed impedance readout with wireless connectivity was implemented and tested at a range of 10 - 12 meters in a lab setting. To evaluate the sensor response to deformation, yaw, pitch, and roll movements were performed to the head's maximum range of motion. The sensors showed significant changes in impedance with yaw/roll resulting in asymmetric changes (10 % - 15 %) and pitch inducing a larger change (15 % - 20 %) due to greater neck flexion. The proposed eutectogel strain sensors can also be used to monitor other body motions with applications in the assessment of gait and mobility impairments, cognitive function decline, or human-machine interface.

Keywords: Neural Networks and Fuzzy Logic, Machine Learning at the Edge, In-Memory Computing Circuits and Systems
Abstract: This paper presents Binary Insertion Sort (BIS), a parallel-friendly sorting algorithm optimized for hardware implementation. By enabling up to k = ⌈log2(N −1)⌉ concurrent binary searches, BIS targets a theoretical time complexity of O(N ), offering an efficient alternative to comparator-intensive designs. Comparative evaluations against state-of-the-art hardware sorting methods, including DL Sort and OWS, show that BIS reduces comparison operations by up to 50% relative to DL Sort while requiring only O(log N ) comparators, significantly lowering hardware complexity. Although OWS achieves minimal data movement, its strict dependence on bit-width and input size limits its general applicability. BIS, by contrast, provides a more flexible and scalable architecture, balancing performance, resource efficiency, and adaptability. These qualities position BIS as a strong candidate for integration in real-time and resource-constrained systems.

Keywords: Neuromorphic System Algorithms and Applications, Machine Learning at the Edge, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Network intrusion detection is crucial for securing data transmission against cyber threats. Traditional anomaly detection systems use computationally intensive models, with CPUs and GPUs consuming excessive power during training and testing. Such systems are impractical for battery-operated devices and IoT sensors, which require low-power solutions. As energy efficiency becomes a key concern, analyzing network intrusion datasets on low-power hardware is vital. This paper implements a low-power anomaly detection system on Intel’s Loihi and Brainchip’s Akida neuromorphic processors. The model was trained on a CPU, with weights deployed on the processors. Three experiments—binary classification, attack class classification, and attack type classification—are conducted. We achieved approximately 98.1% accuracy on Akida and 94% on Loihi in all experiments while consuming just 3 to 6 microjoules per inference. Also, a comparative analysis with the Raspberry Pi 3 and Asus Tinker Board is performed. To the best of our knowledge, this is the first performance analysis of low power anomaly detection based on spiking neural network hardware.

Keywords: Hardware-Software Co-Design, AI Digital Hardware, Accelerators, and Circuits, Machine Learning at the Edge
Abstract: This paper introduces OrganoSens, integrating organic electronics, in-sensor processing, and weightless neural networks to address key limitations in wearable biosensors. By leveraging organic thin-film transistors, the system achieves flexibility, biocompatibility, and low power consumption while maintaining reliable biosignal classification under low-power conditions. An innovative analog preprocessing pipeline efficiently extracts features from ECG and EEG signals, while the specialized computing framework ensures robust operation despite power constraints. Experimental Simulations across ECG and EEG datasets demonstrate competitive accuracy with a 100x smaller memory footprint than CNNs, validating its potential for low-power, wearable health monitoring.

Keywords: Neuromorphic Circuits and Systems, In-Memory Computing Circuits and Systems, Neural Learning Circuits & Systems
Abstract: Ferroelectric field-effect transistors (FeFETs) are emerging to be a promising candidate for low-power in-memory compute based platform design for accelerating AI workloads. However, device-circuit non-idealities and variations due to device scaling pose significant challenges. The paper reviews recent developments in this field related to in-depth characterization of such variabilities in industry standard FeFETs and discusses the interplay of non-linearities in programmable conductance states, device-to-device and cycle-to-cycle variations with device scaling. We outline the design of variation-tolerant neuromorphic hardware accelerators through hardware-software-neuroscience co-design strategies that considers such non-idealities during the training process.

Keywords: Secure AI Hardware, Neuromorphic Circuits and Systems
Abstract: On-chip learning refers to the process of training or updating machine learning models directly on specialized hardware, rather than relying on external computational resources such as CPUs or GPUs. On-chip learning offers reduced latency, energy efficiency, privacy, and adaptability. Hence, on-chip learning is a promising approach for enabling intelligent decision-making and adaptability in edge and IoT devices while addressing the challenges posed by limited resources and data privacy concerns. One of the main features of on-chip learning involves adapting synaptic weights within a Spiking Neural Network (SNN), allowing dynamic adjustments of the network's behavior to align with desired outcomes. Such adaptability is a double-edged sword, as it opens doors for potential security vulnerabilities. Unaddressed security risks in on-chip learning could lead to a wide range of threats, including data leaks, unauthorized access, and even adversarial manipulation of the learning process. In this work, we demonstrate a successful power side-channel attack (SCA) targeting a quantized SNN deployed on the CW305 FPGA using ChipWhisperer. Our analysis reveals consistent power leakage patterns correlated with neuron updates, enabling attackers to infer internal model attributes without accessing model weights or inputs. Furthermore, this manuscript will outline safeguards and mitigation strategies to address these security concerns.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: The C/ID methodology has been used as a baseline to develop analog design automation algorithms for implementing and optimizing design of LC Voltage Controlled Oscillators (LC VCOs). While the existing algorithms are mostly developed to design basic analog circuits in an iterative way, this article expands the existing algorithms to automatize design of LC VCOs at low computational complexity costs. The complex trade-offs among different design parameters in LC VCOs, such as oscillation frequency, power dissipation, phase noise (PN), and tuning range, has made design of this type of circuits very challenging. A systematic approach will be described to map all the key spec parameters of LC VCO circuits into a proper design space, based on which effective design algorithms will be developed. Several design examples have been provided to demonstrate effectiveness and accuracy of the developed algorithms. Simulation data performed in 22 nm FDSOI technology show that the proposed approach results in LC VCO designs with less than 5% error in their center frequency and better than ±1 dBc/Hz accuracy in their PN compared to targeted specifications.

Keywords: Analog Circuits and Systems, Communications Circuits, Theory and Applications, Other Analog/RF Circuits and Systems
Abstract: The advancement of circuit parameter optimization has allowed achieving the optimal configuration of a pre-defined set of topologies. This project introduces SymXplorer, a topology exploration framework designed to systematically synthesize novel circuit topologies through symbolic modeling of analog circuit components. The framework is component-agnostic, capable of exploring architecture-level circuits. SymXplorer integrates stability checks and high-order filter exploration within a user-friendly application program interface (API). Moreover, we include Python wrappers to automatically size the circuits using open-source circuit simulators with Bayesian optimization or evolutionary algorithms. We conclude that Bayesian optimization performs better for circuits where the simulations take a long time, whereas simple schematic-level sizing problems converge faster with evolutionary algorithms. In a case study, we identify and design novel third-order low-pass filters (LPF) using a customized multi-feedback transimpedance amplifier topology. The prototype filter is designed for direct conversion wireless receivers and has a bandwidth of 10MHz. The toolbox is open-sourced and includes example circuit templates for promising topologies to encourage further innovation.

Keywords: Analog Circuits and Systems, Wireless Charging and Energy Harvesting
Abstract: This paper introduces a model for leakage currents in linear integrated charge pumps, along with the corresponding design procedure. The model accounts for leakage in both capacitors and switches, and it analyzes its effect on the circuit parameters such as conversion ratio, power density, and conversion efficiency. Various design trade-offs emerge when selecting different devices within a given fabrication technology, as well as when comparing different fabrication technologies. Specifically, the paper explores the performance differences between implementing the same circuit in a conventional 65-nm silicon-oxynitride polysilicon-gate process and in a 28-nm high-k metal-gate process. The simulation results validate the model and quantify the improvements in power density and conversion efficiency achieved in the high-k process, owing to enhanced device performance and reduced leakage currents.

Keywords: Regulators, References and Reliability Methods, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: Nearly all analog and RF circuits require biasing for which reference circuits provide. This paper presents a node agnostic design methodology that covers critical device selection, transistor sizing, finding multiple solutions within the reference circuit, and excludes all undesired solutions using a start-up circuit. A Bandgap Reference (BGR) was optimized using this process node agnostic design methodology for a space constrained application and was found comparable to other BGR designs within the literature. The designed BGR has the smallest footprint among those compared, 0.000723 mm2, shows a worst case TC of 73.0 ppm/°C over -40 °C to 125 °C for a 1.8 V ± 10% supply without trimming, worst case LS of 5.44 %/V, and worst case PSR of -25 dB at 100 Hz and 1 MHz. The yield for all parameters was found to be greater than 95% (p=0.01, n=500).

Keywords: AI Digital Hardware, Accelerators, and Circuits, Artificial Intelligence for Complex Networks and Nonlinear Systems
Abstract: Abstract—In this paper, we propose an efficient and robust framework for estimating leakage power while considering statistical variations in process parameters, supply voltage, and temperature (PVT) in FinFET-based digital circuits. Extensive testing reports an average error of less than 1% in the ML models for standard digital cells, with an average MAPE (Mean Absolute Percentage Error) of 0.764%, 0.770%, and 0.814% in the 7nm, 10nm, and 16nm FinFET technology nodes, respectively, which ensures a highly accurate leakage estimate for larger circuits. Additionally, we investigated the transistor-level approach, which distinctively estimates subthreshold, gate, and body leakage power using only transistor-level models and stacks, and investigated its trade-offs to gate-level models. Using ML techniques, we achieve a speedup of over 400 times compared to HSPICE for the characterization of digital blocks, using which complex cell designs can be analyzed across various input test combinations, significantly saving the time required for extensive simulations.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Other Analog/RF Circuits and Systems
Abstract: In this work, we introduce an automated methodology tailored for the analysis and verification of analog circuit designs, specifically engineered to generate a color-coded visualization of critical DC and transient operating point metrics. During the iterative process of analog design, circuit configurations frequently undergo modifications. Due to the complex, interdependent nature of analog circuits, even minor adjustments to one minor circuit component can inadvertently propagate undesirable effects across other components, particularly under varying Process, Voltage, and Temperature (PVT) conditions. These subtle, often unintended changes can be easily overlooked, given the high transistor count and the susceptibility of manual inspection to human error. To address this weakness, this paper presents a Python-based graphical user interface (GUI) application that interacts seamlessly with the outputs of the design environment. This tool generates a color-coded summary of the operating point data, providing an intuitive visualization that simplifies the identification of performance deviations. In addition to this, the GUI output is structured to allow designers to filter results based on design hierarchy, process variation, temperature, and other relevant corner cases.

Keywords: RF Front-End Circuits, Physical Design, Test, Verifications, Other Analog/RF Circuits and Systems
Abstract: This paper discusses the design automation and optimization of passive lumped element impedance matching networks. 8 different types of such networks, capable of matching between complex loads, are discussed. The automation engine optimizes the design of these networks independent of the technology node, while also considering the finite quality factors of capacitors and inductors. The optimization algorithm was implemented in Python with a TSMC 65 nm technology as a test case, and the code takes around 20-40 seconds to run in an i9 system with 32GB memory.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Other Analog/RF Circuits and Systems
Abstract: This paper presents a low-power, wide dynamic range (DR) PPG readout IC featuring a Time-based quantizer directly embedded in the photodiode driver circuit. Conventional PPG readout architectures, such as TIA or LDC-based approaches, require additional DC suppression loops, leading to increased power consumption, complexity, and limited dynamic range. To solve this problem, the proposed architecture eliminates the need for a separate DC suppression circuit by integrating a linear regulator with an embedded time-based quantizer, enabling efficient and direct current sensing. The proposed design achieves a wide DC dynamic range while maintaining high signal-to-noise and distortion ratio (SNDR). Simulation results demonstrate that the readout circuit achieves an SNDR of 46.2 dB at a DC current of 100 µA, while the linear regulator exhibits fast transient response, ensuring stable biasing for the PPG sensor. Additionally, the VCO-based quantizer provides inherent 1st-order noise shaping, further improving signal acquisition accuracy. The proposed readout IC is implemented with an area of 0.378 mm², demonstrating its feasibility for wearable and biomedical sensing applications.

Keywords: Other Sensory Circuits and Systems, Technologies for Smart Sensors, Sensor Interface Circuits and Microsystems
Abstract: The paper presents a system-level design of a current-adjustable, nanosecond-range pulsed laser driver with a high repetition rate optimised ultra-low photon generation. The design comprises two adjustable constant current sources that independently generate a DC bias current and a pulse current, which are combined and then driven to the laser diode. A GaN FET-based switch generates the current pulses from a Howland current pump. The circuit is simulated and verified with two laser diode models developed in LTspice, and results are analysed to evaluate the performance and stability of the system.

Keywords: Sensor Interface Circuits and Microsystems, Other Sensory Circuits and Systems
Abstract: This paper presents design and comprehensive analysis of a new robust front-end circuitry with tunable dead time and low noise for single photon avalanche diodes (SPADs) implemented in a standard 180 nm CMOS process. Besides accelerating avalanche detection and rapid quenching, the design incorporates a hold-off time and reset time control feature that facilitates the tuning of dead time in order to mitigate the tradeoff between photon detection efficiency (PDE), maximum photon count rate, and afterpulsing effect. We achieved a nominal deadtime of approximately 2.12 ns, with the capability of dead time tuning over a wide range between 1.9 ns and 40 ns, which corresponds to a maximum count rate of 25 Mcps to 526 Mcps. A comprehensive analysis was conducted by thoroughly examining the effects of temperature varying over a wide range from -40◦C to 150◦C, hold-off capacitors varying from from 2 pF to 24 pF, fabrication process corners, and transistor sizes on dead time. Quenching transition of 47.5 ps at excessive bias voltages of 5 volts, and final reset of 52 ps were achieved.

Keywords: Internet of Things (IoT) Theory and Systems, Other Sensory Circuits and Systems
Abstract: The vulnerability of autonomous vehicle (AV) systems to Global Positioning System (GPS)-based attacks presents a significant challenge in ensuring reliable navigation and sensor integrity. This work addresses the lack of modifiable GPS data output in CARLA which limits the evaluation of sensor vulnerabilities under different attack scenarios. To overcome this limitation, we introduce a novel unbounded GPS navigation framework within the CARLA simulator. A Proportional-Integral-Derivative (PID) controller is integrated with the GPS approximation method to improve navigation performance under adversarial conditions. The framework has been tested under two GPS attack models, demonstrating its ability to handle small deviations while revealing limitations in correcting larger biases. Experimental results demonstrate successful navigation in both straight-line and waypoint-based scenarios, establishing a foundation for future work focused on mitigating sensor manipulation through reverse engineering techniques and improved GPS tracking systems.

Keywords: Internet of Things (IoT) Theory and Systems, Other Sensory Circuits and Systems
Abstract: Advancements in GPS technology have significantly enhanced navigational accuracy, yet they remain vulnerable to spoofing attacks. This paper presents a spoofing attack capa- ble of manipulating the trajectory of an autonomous vehicle (AV) equipped with a global positioning system and inertial measurement unit system. This is achieved without triggering detection mechanisms that rely on Kalman Filter’s innovations- based detection. In recent literature, randomized normalized innovation squared (NIS) detection alarm has been used to detect GPS spoofing. However, our proposed algorithm, quickest attempt attack (QuAck), identifies that an attacker can bypass randomized NIS in a realistic threat model. This result highlights the need for further investigation to ensure the security of AV’s navigational perception system.

Keywords: Physical and Chemical Smart Sensing Systems, Analog Circuits and Systems, Analog, Digital and Mixed Signal Processing
Abstract: This paper presents an integrated current mode feature extraction system. The system includes a sign bit generator, an integrator, a peak detector, a pulsewidth determiner, and a digital signal generator. The feature extractor was verified through simulations for a SiPM output signal up to 2.86 MHz. The system had an overall power consumption of 550 µW.

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems, Digital Integrated Circuits
Abstract: This paper presents a compact and energyefficient Direct Current-to-Digital Converter (DIDC) for realtime on-chip current sensing, implemented in 180nm CMOS technology using 1.8V devices. The proposed design eliminates the need for bulky resistors or explicit analog-to digital converter employing a fully MOSFET-based architecture with a successive approximation register (SAR)-controlled compensation loop and a binary-weighted R-2R digital-to-analog converter (DAC). The system targets power delivery networks (PDNs), enabling non-intrusive monitoring of IR drop to infer local current levels with high accuracy. Simulation results demonstrate reliable operation across a wide current range 0A to 9A, with robust performance over temperature variations from −10 ◦C to −120 ◦C. The design achieves 9-bit resolution at 12MHz with a total power consumption of only 365 μW.

Keywords: Integrated Biomedical Systems, Linear and Non-linear Analog Systems, Sensor Interface Circuits and Microsystems
Abstract: In this article, a previously published amplifier-less potentiostat architecture is further examined. Starting with a linearized model, the impact of the most important parameters is studied taking in account the electrodes-solution electrochemical interface. A detailed model is obtained and thoroughly verified, and recommended operating conditions are given for certain limit load conditions. Then, a more complete non-linear model is developed to take in account the measurement uncertainty introduced by the circuit non-linear components. This non-linear model is compared to a time domain description of the circuit and it is verified that it can predict the non-linear behavior with a precision better than 20%. This result enables the circuit designers to compensate for these effects and ultimately reduce the overall measurement uncertainty.

Keywords: Biomedical Signal/Image Processing, Point-of-Care Biomedical Diagnostics
Abstract: Interictal epileptiform spikes and high frequency oscillations (HFOs) have proven to be promising neuro biomarkers for seizure onset zone (SOZ) identification in drug-resistant epilepsy. This study presents a sparse signal processing based denoising model for epileptiform spikes. The model was trained on expert-labeled events to remove artifacts and spurious detections from the initial candidate spike pool captured using an amplitude threshold-based detector. We hypothesize that interictal spikes exhibit a sparse representation with a limited number of atoms in analytical dictionary, whereas artifacts, due to their unstructured waveshape, lack such a representation. We employed orthogonal matching pursuit (OMP) with a Gabor analytical redundant dictionary for event representation and Random Forrest (RF) classifier for event classification. The optimal model was further evaluated over the intracranial EEG (iEEG) from 29 subjects during intraoperative monitoring (IOM). Denoising method significantly improved the SOZ delineation of spatial distribution of spike (36% to 52% in IOM). Additionally, we included HFO analysis results to provide further comparison with spikes yielding an average denoised SOZ ratio of 69% in IOM. These advancements could enhance clinical decision-making by offering reliable initial assessments during a brief intraoperative recording.

Keywords: Point-of-Care Biomedical Diagnostics, Analog Circuits and Systems, Other Areas in Biomedical Circuits and Systems
Abstract: This work presents an exploration of portable microwave tumor detection systems. A transportable system is created to detect different sizes of tumors in breast phantoms. The system has an inherent resonant frequency that shifts to higher frequencies when a larger tumor is present. In order to have higher precision, a machine learning classification algorithm is used and enables 97.2% accuracy when detecting the difference between an 8mm tumor and no tumor.

Keywords: Biomedical Signal/Image Processing, Signal Processing Theory and Methods, Other AI and Edge Topics
Abstract: This study presents a novel, computationally efficient approach for ECG envelope extraction using the Residue Number System (RNS), a modular arithmetic framework. By decomposing ECG signals into residue components, the proposed method enables closed-form algebraic envelope estimation without relying on traditional transformations or filtering techniques. Comparative analysis with conventional methods— such as Hilbert, wavelet, and Shannon energy-based envelopes— demonstrates that the RNS approaches achieve superior accuracy and robustness in R-peak detection, particularly under noisy conditions. These results highlight the potential of modular arithmetic for efficient ECG analysis in embedded and wearable health monitoring systems.

Keywords: Other Areas in Biomedical Circuits and Systems, Neural Learning System Algorithms and Applications, Biomedical Signal/Image Processing
Abstract: We developed biophysically realistic 10,000 cell neuronal network models of three cortical regions to investigate microcircuitry features that support beta and gamma oscillations that are thought to subserve communication in the brain. The model single cells and networks were constrained by in vitro and in vivo cellular and synaptic neurophysiology data. Several microcircuit parameters were found to have a significant impact on the oscillation characteristics: inactivation of short-term presynaptic plasticity, and of electrical and chemical synapses between inhibitory interneurons had a profound effect individually on oscillatory power, as did the mutual inhibition motif between the interneurons.

Keywords: Biomedical Signal/Image Processing, Machine Learning at the Edge
Abstract: This study presents a novel approach to phonocardiogram (PCG) signal classification using hyperdimensional computing (HDC) with hybrid feature extraction and Sobol-based hypervector encoding. Our method transforms heart sound signals into high-dimensional hypervectors by extracting key audio features, such as Mel-frequency cepstral coefficients (MFCCs), zero-crossing rate (ZCR), spectral contrast, and chroma features, followed by quantization and encoding into high-dimensional space. The resulting hypervectors are then classified using multi-centroid class representations, generated via k-means clustering, and evaluated through cosine similarity. Our approach achieves rapid inference, robust noise tolerance, and lower computational complexity compared to traditional machine learning methods. The hybrid feature encoding technique effectively captures both spectral and temporal characteristics of PCG signals, enhancing classification accuracy and consistency. We evaluate our model’s performance using confusion matrices, inference time analysis, and energy efficiency estimation on a 3W TinyML embedded device. Our refined classifier demonstrates an overall accuracy of 83%, with an average inference time of 1.15 ms per sample, and energy consumption as low as 0.0035 Joules per classification. These results emphasize the potential of our HDC-based approach for reliable, real-time, and low-power diagnostic applications in embedded and wearable biomedical devices.

Keywords: Biomedical Signal/Image Processing, Signal Processing Theory and Methods, Neural Networks and Fuzzy Logic
Abstract: This paper introduces a new integrated framework that unites Graph Signal Processing methods with Graph Convolutional Networks for N- and O-glycosylation site prediction in proteins. Our approach builds dual graph representations from residue-level embeddings based on both sequential and proximity-based relations to model local and distant dependencies. Spectral transforms viz., Graph Fourier, Cosine, and Scattering Transforms are used to preprocess the node features before passing them to parallel Graph Convolutional branches. Saliency analysis also proves evidence towards significant residues impacting predictions. In the case of N-linked glycosylation, our best-performing model achieves MCC of 75.96% and an F1 score of 78.89%, while in the case of O-linked glycosylation, it achieves MCC of 52.21% and an F1 score of 57.71%. Experimental evidence demonstrates that the new method performs competitively across a range of measures, an indication of its usefulness in enhancing glycosylation site prediction.

Keywords: Linear and Non-linear Analog Systems, Analog Circuits and Systems
Abstract: The discrete-time hyperchaotic Generalized Henon Map (GHM) developed by Baier and Klein provides N-1 positive Lyapunov characteristic exponents, where N is the system order. Extending the map to higher dimensions only requires additional delays of one computed state; furthermore, only one nonlinear component is required. These features make the GHM an excellent candidate for generating electronic discrete-time arbitrary-dimension hyperchaos. A tenth-order GHM was realized using a general modular approach to autonomous electronic discrete-time chaotic maps based on an analog shift register (ASR). The maximum order that can be realized is limited only by ASR performance. The tenth-order GHM circuit appears to be the highest-order electronic implementation of discrete-time hyperchaos described in the research literature.

Keywords: Other Signal and Image Processing, Adaptive Signal Processing with Deep Learning, Streaming and Human-Computer Interactions
Abstract: Brain-Robot Interaction (BRI) enables individuals to control robotic systems and automated devices through brain activity, facilitating advancements in human-computer interaction (HCI) and human-robot interaction (HRI). As electroencephalogram (EEG) and other physiological signals serve as critical communication channels in brain-computer interfaces (BCIs), their efficient processing and classification remain pivotal for improving autonomous system control and assistive robotics. A multi-modal deep learning approach is proposed in this paper, in which discrete wavelet transforms are integrated for signal pre-processing, and numerical biomedical signals are converted into 2D and 3D representations to enhance feature extraction. The study applies deep learning techniques to EEG datasets and human activity recognition (HAR) recordings, demonstrating enhanced classification accuracy through wavelet-based feature extraction. The findings emphasize the potential of multi-modal deep learning in advancing BRI applications, optimizing real-time human intent recognition, and improving the robustness of autonomous systems.

Keywords: Image, Video and Multi-Dimensional Signal Processing, Other AI and Edge Topics
Abstract: Mobile phone processors have emerged as a key driving force in the evolution of embedded systems, thanks to their versatility, power efficiency, and cost-effectiveness. Low-cost platforms like the Raspberry Pi family are equipped with high-performance multi-core CPUs and GPUs, making them well-suited for real-time image processing tasks. This paper introduces a GPU shader method for detecting moving objects and measuring their speed using a constant-rate series of sequential images, such as live video feeds or recordings from existing traffic cameras. The system employs the industry-standard, non-vendor-specific OpenGL ES on affordable embedded systems. The CPU manages data flow to the GPU shaders, which identifies changes in pixels across frames to detect potential moving objects. The displacement of each object is then calculated, mapped into a practical distance, and returned to the CPU. This approach was implemented on a low-cost Raspberry Pi 4, successfully extracting speed data from 720p video at 10 FPS. Additionally, the code is easily portable to newer, faster embedded platforms, enabling even higher data rates.

Keywords: Analog Circuits and Systems, Analog, Digital and Mixed Signal Processing, Converters, ADC, DAC and others
Abstract: This paper analyzes three signal transforms in analog domain (i) Discrete Cosine Transform (DCT), (ii) Discrete Hadamard Transform (DHT), and (iii) Haar Transform for their effectiveness in analog image compression, i.e., maintaining acceptable image quality and the ease of realizing them in analog domain. The work is motivated by the need for energy-efficient analog image compression methods that can be used in internetof- things (IoT) devices and other energy constrained devices for data collection for machine learning (ML) applications.

Keywords: Adaptive Signal Processing with Deep Learning, Neural Learning System Algorithms and Applications, Linear and Non-linear Analog Systems
Abstract: Fast hyperparameter search in nonlinear time-variant systems is needed as traditional adaptive methods like Normalized Least Mean Square (NLMS) often exhibit slow convergence and high sensitivity to dynamic variations. We propose Centroids Pull Search (CPS) and Multi-Centroid (MC) Artificial Intelligence loops (AI-loops), a hybrid framework that combines non-autoregressive (NAR) and autoregressive (AR) update strategies in a stage-wise fashion. In the early phase, CPS operates as a regressive, non-autoregressive method: parameter values bounce between multiple centroids based on the error of the current iteration, without attenuation or memory, enabling aggressive exploration of the parameter space. As estimation progresses, CPS transitions into a non-regressive, autoregressive phase, where an attenuation factor is introduced to stabilize updates. This attenuation smooths parameter evolution, causing updates to increasingly depend on previous estimates, enabling convergence without revisiting prior errors. AI-loops further enhance this adaptive framework by integrating lightweight neural networks that infer optimal hyperparameter refinements in real time. We evaluate CPS, AI-loops, and their hybrid integration with Guided Random Search (GRS) against NLMS in polynomial coefficient estimation, whose input is a 128-carrier Orthogonal Frequency Division Multiplexing (OFDM) signal. Simulation results show that AI-loops converge 20 iterations faster than CPS and achieve a 4.5 dB improvement when restricted to 100 iterations in a 3rd order polynomial with uniformly distributed coefficients in the range [-1,1].

Keywords: Deep Learning for Multimedia, Neural Learning System Algorithms and Applications
Abstract: Crack segmentation plays a vital role in assessing the structural integrity and safety of pavements and concrete surfaces. While traditional deep learning models have achieved high accuracy in this domain, they require extensive labeled data and lack adaptability. This paper investigates the potential of vision–language models (VLMs) for crack segmentation, focusing on two recent frameworks: Generalized Segmentation via Multimodal Large Language Models (GSVA) and Text Prompt-able Surgical Instrument Segmentation (TP-SIS). We evaluate their performance on two benchmark datasets—DeepCrack and Crack500—using various natural language prompts and compare them to well-established CNN-based models including UNet++, LinkNet, and MANet. Our results show that TP-SIS achieves competitive, and in some cases superior, performance compared to CNNs on Crack500, while GSVA shows promising generalization on DeepCrack with minimal fine-tuning. We also find that prompt phrasing significantly influences VLM performance, with general prompts consistently yielding better segmentation results. Although VLMs do not yet outperform specialized CNNs across all metrics, their adaptability, prompt-based control, and scalability make them promising tools for future crack detection.

Keywords: Other Power Circuits and Systems, Neural Networks and Fuzzy Logic, Other AI and Edge Topics
Abstract: Accurate monitoring of Combined Cycle Power Plants (CCPPs) is key to optimizing efficiency, cutting costs, and ensuring reliable energy. Traditional regression-based methods yield continuous outputs, which may limit real-time usability. This study introduces a classification-based approach to categorize power output into discrete levels for more actionable insights. It also incorporates an Autoencoder-based anomaly detection system to identify faults and performance issues. Ensemble models such as LightGBM and Gradient Boosting enhance classification accuracy, while the Autoencoder achieves high recall with few false positives, outperforming methods like Isolation Forest and Elliptic Envelope. The integrated framework improves predictive maintenance and real-time decision-making in CCPPs and offers scalable applications across industrial energy systems.

Keywords: Regulators, References and Reliability Methods, Analog Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: This paper presents a detailed PSRR analysis of the NMOS zero temperature coefficient (ZTC) operating point-based voltage reference circuits and a NMOS ZTC operating point-based supply voltage regulation scheme. The proposed voltage regulation scheme is self-referenced and maintains a stable supply voltage across temperature and voltage variations. Furthermore, the proposed voltage regulation scheme maintains consistent voltage headroom for MOSFETs by tracking the process induced changes in the reference voltage, thereby, enhancing the PSRR performance across process design corners.

The proposed design concepts are validated with the simulation results obtained from circuits designed in UMC 65nm CMOS process. For the NMOS ZTC bias point based pseudo regulated reference design, simulated Vref and IQ at 27degC are 780.6 mV and 8.872uA, respectively. The mean temperature coefficient of Vref is 55.3ppm/degC, over a temperature range of -40degC to 125degC. Simulated typical and worst case PSRR at 10Hz are -110.63dB & -85dB, respectively. The design achieves a typical line sensitivity of 0.00038%/V over a Vdd range of 3V to 4V.

Keywords: Wireless Charging and Energy Harvesting, Analog Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: A low-minimum-start-up-voltage, low-input-power, small-formfactor self-oscillating voltage doubler in 7nm FinFET has been demonstrated. By introducing back-end MOM capacitors, small footprint can be obtained. Additionally, minimum design of the scaled FinFET transistors allow low power consumption with low cold start up voltage. Test chip has been designed and manufactured in 7nm RF FinFET. The chip area is 0.00006 mm². Measured results showed that the minimum cold startup voltage is 110 mV where its input power is 12 pW.

Keywords: Regulators, References and Reliability Methods, Analog Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: We present a folded bandgap voltage reference (FBGR) that provides an output voltage of 366.35 mV. Designing startup circuits for sub-1V current-mode bandgap voltage references is inherently challenging due to multiple operating points at low currents. Our proposed design simplifies this process by featuring only two operating points, significantly easing the startup circuit design. Additionally, the circuit retains valuable PTAT current necessary for various applications without the need for additional circuitry. Furthermore, it minimizes the number of error sources, resulting in an output offset of 166.87 µV over 500 Monte Carlo simulations. The folded bandgap configuration also incorporates curvature compensation by injecting non-linear current into the larger diode, achieving an impressive accuracy of 3.14 ppm/oC across a wide temperature range of -40 C to 120 C in TSMC's 65nm process, all while occupying a compact area of 0.028 mm^2

Keywords: Other Analog/RF Circuits and Systems, Physical Design, Test, Verifications, Other Sensory Circuits and Systems
Abstract: Renewable energies have gained much attention and have expanded their use considering the cost and the impact on climate. To reduce carbon emissions, solar energy is one significant option. The solar energy harvesting sites can be located in remote, unpopulated areas. However, the sites can have an impact on the ecosystem. The study explores the energy harvest and the energy remaining in a harvesting cage in terms of light intensity and developed voltage. Miniature solar cages have been modelled and built for the study. The prior results showed wide intensity variation inside the cage, whereas the generated voltage has a narrow variation. In the current study, intensity variation has been investigated in a controlled environment, which shows even more reduction in illumination intensity, indicating a possible impact on an assumed biological system residing inside the built cage.

Keywords: Analog Circuits and Systems, Other Power Circuits and Systems
Abstract: This paper describes a method for maximizing the power delivered to the rectifier in energy harvesters. It is demonstrated that there is an optimal turn-on time for rectifiers to maximize power transfer from the harvester. Next, a maximum power point tracking methodology based on rectifier turn-on time (RTOT-MPPT) is developed for triboelectric energy harvesters. The primary advantage of the proposed approach is the relative independence of the optimal turn-on time on the frequency and peak voltage of the harvester output. Thus, the proposed RTOT-MPPT method reduces the complexity of power tracking and can be efficient for a wider range of harvesters. The method is implemented for a triboelectric harvester and simulated in a 180nm industrial HV-CMOS process, demonstrating that 34% higher power is delivered to the rectifier in each cycle.

Keywords: Power Management of Electric Vehicles, Other Power Circuits and Systems
Abstract: This paper presents the design of a compact Power Management Integrated Circuit (PMIC) utilizing 650 V Enhancement-mode (E-mode) p-GaN technology for medium power Electric Vehicles (EV) charging applications. The proposed PMIC achieves Integration Level 3 by incorporating a Pulse Width Modulation (PWM) generator, a two-stage fast gate driver, a high-voltage power switch, and a current-mirror sensor. Post-layout simulations conducted in Cadence Virtuoso assess the circuit's performance under varying temperature conditions. The PMIC operates at 1 MHz, with an output power of 1kW and 97% of efficiency. The PWM generator features a wide controllability range from 5% to 95% duty cycle, while the gate driver achieves rise and fall times of 9.45ns and 14.45ns, respectively. The total active area, including pads, is 2.94mm².

Keywords: Hardware Security, Physical Design, Test, Verifications, Physical and Chemical Smart Sensing Systems
Abstract: Due to minute discrepancies in process conditions, material properties, and geometrical defects, all CMOS devices have statistical variations in electrical characteristics. These unwanted variations carry features unique to a given process and cannot be imitated. In particular, native traps at interfaces of semiconductors and defects in thin-film devices can be used to enhance hardware security at the chip level. Such traps and defects, and their energetic distributions, can be probed on-chip by pulsed I-V characterization step that can generate a unique transient response with identifiable features. Trap properties extracted from such native or engineered current transients can be used to establish new forms of process identification and reliability monitors. In this paper, we propose to use pulsed current spectroscopy (CTS) technique and a proven Bayesian deconvolution approach that can efficiently capture trap properties to monitor such tamper-resistant digital 'fingerprints' for process identification and chip reliability. A proof-of-concept study based on simulated MOSFET drain transients is also presented to verify its practical use in CMOS devices. The proposed CTS approach can be used to enhance hardware security by superior process identification, avoiding supply-chain attacks based on suboptimal materials and counterfeiting of critical circuit elements via short-term (simmus to second) current transients. It can also be used to monitor overall chip reliability, thanks to the long-term episodic comparisons of trap generation and evolution.

Keywords: Other Beyond CMOS Topics, Hardware Security, Information Theory, Coding and Security
Abstract: Single Electron Transistor (SET) is a nanoscale device that exploits quantum tunneling and the Coulomb blockade to control electron flow with high precision. This paper reviews single-electron technology and introduces novel SET-based logic gates designed for efficient computational applications. These proposed logic gates are subsequently utilized to implement finite field multiplication. To enable the integration of SET-based logic, several multiplication architectures are analyzed and adapted. The complexities of the resulting multipliers in mathbb{F}_{2^8} are evaluated and benchmarked against conventional MOS implementations, demonstrating significant improvements in spatial complexity for the presented designs.

Keywords: Digital Integrated Circuits
Abstract: Aging and reliability are becoming greater concerns as transistors densities exceed a billion devices per chip. Adaptive circuit techniques such as adaptive body biasing can alleviate these issues, but still require adjustments to be done at a course grain approach due to the need of voltage generators for each independently applied bias. In this work, we evaluate the threshold voltage programmability of a double gate transistor with a ferroelectric layer integrated into the back gate. The front gate is used for CMOS logic operation, enabling threshold voltage programmability of the transistor though the ferroelectric layer. We developed a simulation framework compatible with existing EDA tools and evaluated this proposed device structure as a novel adaptive body biasing scheme which replaces the traditional body bias with a ferroelectric material. This scheme alleviates the need for multiple voltage generators on a chip, thereby allowing for much finer-grain adjustments to be made in order to improve overall efficiency.

Keywords: Other Beyond CMOS Topics, MEMS/NEMS and Nano-Electronics, Other Wireless and Communications Topics
Abstract: This paper presents an energy-efficient on-chip clock driver design, enabled by copper/cobalt (Cu/Co) multilayer-based low-RF-loss on-chip metaconductors, for applications in millimeter wave bands including the 28-GHz n257/LMDS 5G communication. Cu/Co metaconductors in our earlier research have demonstrated lower conductor loss, reduced signal dispersion, and lower thermal noise as compared to conventional Cu-based coplaner waveguides (CPW), and has shown better quality factor (Q) for on-chip inductors. In this work, we co-design CMOS circuits with metaconductor based interconnects for mm-Wave clock driving applications, which can be extended to various wireless and wireline applications including UCIe in future. Simulations using ANSYS HFSS show approx40% better RF resistance and possibilities of 16-21% denser interconnects (through cross-talk analysis), while circuit simulations using a 65 nm technology node shows >27% improvement in power consumption by adopting Cu/Co-based metaconductors instead of Cu interconnects.

Keywords: Sensor Interface Circuits and Microsystems, Point-of-Care Biomedical Diagnostics, AI-IoT Systems and Applications
Abstract: Biosensor innovation is advancing, yet structured, data-driven patent analysis remains limited. We introduce an API-driven retrieval and classification framework, leveraging the PatentsView API to collect and categorize 138 biosensor patents since 2019. A keyword-based classification scheme and network and trend analysis identify key technological domains, innovation trajectories, and collaboration networks. Findings show leading contributions from Illumina, Inc., IBM, and Duke University. Patent filings declined in 2021 due to pandemic-related disruptions but rebounded from 2022 to 2024, indicating renewed research efforts. Faster patent grant timelines suggest an accelerating innovation cycle, with AI-driven biosensing, wearable monitoring, and biocompatible materials emerging as key trends. However, commercialization challenges persist for graphene-based and nucleic acid biosensors. This study provides a scalable, replicable methodology with open-source code and visual analytics, enabling automated patent retrieval, computational analysis, and interactive visualization for future research.

Keywords: Hardware Security, Technologies for Smart Sensors, Other Analog/RF Circuits and Systems
Abstract: Digital image watermarks as a security feature can be derived from the imager’s physically unclonable functions (PUFs) by utilizing the manufacturing variations, i.e., the dark signal non-uniformity (DSNU). While a few demonstrations focused on the CMOS image sensors (CIS) and active pixel sensors (APS), single photon avalanche diode (SPAD) imagers have never been investigated for this purpose. In this work, we have proposed a novel watermarking technique using perimeter gated SPAD (pgSPAD) imagers. We utilized the DSNU of three 64 × 64 pgSPAD imager chips, fabricated in a 0.35 µm standard CMOS process and analyzed the simulated watermarks for standard test images from publicly available database. Our observation shows that both source identification and tamper detection can be achieved using the proposed source-scene-specific dynamic watermarks with a controllable sensitivity-robustness trade-off.

Keywords: Emerging Memory and Memristor, In-Memory Computing Circuits and Systems, Neuromorphic Circuits and Systems
Abstract: This study presents the simulation and analysis of a novel three-terminal Gated Ferroelectric Tunnel Junction (GFTJ) using technology computer-aided design (TCAD) tools with fitted experimental values from the fabricated Ferroelectric Tunnel Junction (FTJ). The proposed device leverages ferroelectric polarization and tunneling electro-resistance (TER) effects to achieve multiple intermediate resistance states, enabling lowpower multi-state memory applications. Additionally, the fabrication and testing of an FTJ are investigated, laying the groundwork for G-FTJ integration. A neuromorphic application is proposed, demonstrating its potential in advanced computing systems.

Keywords: In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Other Beyond CMOS Topics
Abstract: Vision transformers (ViTs) have emerged as one of the most popular computer vision models, achieving remarkable performance in image recognition. However, ViTs require large scale, high-dimensional matrix computations, and traditional digital accelerators, such as graphics processing units (GPUs) have memory bandwidth limitations, leading to higher latency, increased energy consumption, and larger area. To address this challenge, this paper proposes a memristor-based analog accelerator. The architecture leverages memristor crossbar arrays for in-memory computing, reducing data movement and improving computational efficiency. Additionally, a digital circuit accelerator is designed and optimized at the 5 nm technology node for comparison. Results show that the design achieves one order of magnitude reduction in area, 18× reduction in delay, and 2× reduction in energy for a patch size of 32×32, compared to the digital counterparts.

Keywords: Machine Learning at the Edge, AI Digital Hardware, Accelerators, and Circuits, Other AI and Edge Topics
Abstract: Pre-trained vision transformers have achieved remarkable performance across various visual tasks but suffer from expensive computational and memory costs. While model quantization reduces memory usage by lowering precision, these models still incur significant computational overhead due to the dequantization before matrix operations. In this work, we analyze the computation graph and propose an integerization process based on operation reordering. Specifically, the process delays dequantization until after matrix operations. This enables integerized matrix multiplication and linear module by directly processing the quantized input. To validate our approach, we synthesize the self-attention module of ViT on a systolic array-based hardware. Experimental results show that our low-bit inference reduces per-PE power consumption for linear layer and matrix multiplication, bridging the gap between quantized models and efficient inference.

Keywords: AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Machine Learning at the Edge
Abstract: The growing demand for matrix multiplication in artificial intelligence must be met with increased tensor computing efficiency and bandwidth improvements. While AI throughput using digital hardware accelerators has advanced, the potential of analog circuits has been largely untapped. In this paper, we introduce a novel Fourier-Accelerated CMOS-based Tensor Engine (FATE) that aims to optimize the high complexity of matrix multiplication with computation and bandwidth efficiencies. First, our design reduces the computational complexity of matrix multiplication from the traditional O(N^3) to O(N^3/f), where f is a number of frequency carriers up to N. Second, our circuit dramatically reduces the bandwidth required for moving vectors by encoding a vector as a summed sine series routed via two physical wires. The test circuit, designed with a 180 nm standard CMOS process, achieves a strong dot product linearity with an R^2 value of 0.94. This work highlights the untapped potential of analog circuits in modern AI, offering a highly efficient solution to a critical bottleneck in AI computation.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Machine Learning at the Edge, AI-IoT Systems and Applications
Abstract: With the rapid advancement of artificial intelligence,Spiking Neural Networks (SNNs) have shown great potential for resource-constrained edge computing systems thanks to SNN's efficient temporal processing and low-power characteristics. However, most existing hardware designs for SNN inference rely on a fixed number of timesteps in spike temporal encoding, limiting SNN's flexibility. In this paper, we present FlexBits-SNN, a RISC-V-based general-purpose processor architecture. It incorporates multiple custom extension instructions along with a variable number of timesteps for spike encoding. FlexBits-SNN accelerates inference in both one-dimensional and two-dimensional SNN networks. The custom instructions,invoked via inline assembly in C,provide greater flexibility compared to traditional processors and support complex SNN architectures. The FlexBits-SNN processor executes SNN inference tasks with an arbitrary number of timesteps and achieves over a 90% reduction in inference time as compared to conventional RISC-V ISA. Performance evaluation under 55nm CMOS process demonstrates a peak energy efficiency of 6.42 pJ/SOP(Synaptic Operation), highlighting its suitability for efficient SNN inference.

Keywords: Digital Integrated Circuits
Abstract: In the IoT era, real-time data classification on small footprint IoT/edge devices requires deploying complex algorithms, such as CNN, on embedded devices. MobileNetV2 CNN architecture is designed in such a way to be executed on resource-constrained embedded devices, while achieving good performance in terms of accuracy and inference time. In this paper, we propose an FPGA-based hardware accelerator for bottleneck residual blocks of MobileNetV2 CNN to further improve various performance metrics on embedded devices. Our embedded hardware accelerator achieves up to 18 times speedup compared to its embedded software counterpart.

Keywords: In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neuromorphic Circuits and Systems
Abstract: The energy consumption of Memristive Dot Product Engine is a major concern for low-energy AI applications. This paper discusses an on-chip, data-independent row pruning scheme for one-hot encoded Spiking Neural Networks (SNN) at the custom circuit level, facilitating dynamic energy management. This scheme can prune a significant number of rows with a marginal performance drop for three machine learning applications. Moreover, the scheme can save energy up to 2 orders of magnitude after running the system for 1000 cycles in pruned mode, compared to the energy cost of the row pruning system.

Keywords: Neuromorphic Circuits and Systems, Emerging Memory and Memristor, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: Recent foundry-based integration of Resistive Random Access Memory (RRAM) with standard CMOS drives interest in developing high-density, low-power Edge-AI accelerators. 1TnR RRAM arrays have shown promise for realizing very low-energy Vector Matrix Multiplication (VMM) computation in the analog domain. On the other end of the spectrum, spiking neural networks (SNNs) promise low-power computing by eliminating energy-expensive data converters. However, mixed-signal circuit designers must account for RRAM nonidealities and innovate circuits that bridge the performance gap between digital ANNs and analog SNNs. This article reviews this area and presents novel multi-level spiking CMOS neurons that easily interface with RRAMs while providing higher-resolution encoding.

Keywords: Neuromorphic Circuits and Systems, Neural Networks and Fuzzy Logic
Abstract: This study presents a new approach at the sample and hold implementation for mitigating sparsity in event driven bitstreams. This unique approach takes advantage of the asynchronous nature of Event Cameras (EC) and tailors the system to behave likewise. In doing so the new hold system reduces redundant input and only creates new input if changes occur, resulting in a system that will work regardless the time sparsity of the EC data. There was an observed increase of 50% in accuracy at low bitstream lengths in temporally sparse datasets.

Keywords: Neuromorphic Circuits and Systems, Neuromorphic System Algorithms and Applications, Emerging Memory and Memristor
Abstract: Neuromorphic electronics take inspiration from the biological brain where synchronization processes, including synchronization of chaos, play an important role. For the analysis and design of such systems, the practitioner needs synchronization criteria that cover memristive coupling circuits and chaotic systems. We show that a criterion based on dissipation theory and Lyapunov's direct method meets these requirements by applying it to a memristive network of Chua's circuits. Here, we show state synchronization depending on a Lipschitz-like condition on the Chua's circuits, passivity properties of the coupling circuits and connectivity properties of the connection topology.

Keywords: Neuromorphic System Algorithms and Applications, Neuromorphic Circuits and Systems, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Spiking Neural Networks (SNNs) leverage biologically inspired learning mechanisms such as Spike Timing Dependent Plasticity (STDP) to modify synaptic weights. This work explores two STDP models: the pair-based rule and the more biologically plausible triplet-based rule. Synaptic update equations for the triplet STDP model are extracted directly from transistor-level SPICE simulations, capturing the dynamics of hardware-implemented synapses. The mathematical model is then incorporated into a Python simulation, providing insights into the feasibility of triplet STDP in neuromorphic hardware and its potential advantages in capturing more complex temporal dependencies in spike patterns.

Keywords: Neural Learning Circuits & Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neural Networks and Fuzzy Logic
Abstract: This paper presents a reconfigurable analog neural network architecture implemented with discrete components for machine learning inference tasks. We use digital potentiometers to store model parameters and digital-to-analog converters to represent input data as DC voltages. The system implements matrix multiplication through the op-amp summer configuration and incorporates ReLU activation functions using active rectifiers. The system achieves nearly the same accuracy as its software counterpart when evaluated on the MNIST validation dataset.We also measure the end-to-end propagation delay, and power consumption. Our results demonstrate the viability of application-specific analog computing for AI tasks. The work highlights the potential of reconfigurable analog hardware for edge computing applications where energy efficiency is paramount.

Keywords: Neural Learning Circuits & Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Analog Circuits and Systems
Abstract: Most analog nonlinear resistive neural networks for machine learning training use doubling input and output neuron nodes to implement negative weights. However, this approach increases network size, modifies the gradient computation, and complicates circuit design. We propose an alternative circuit topology that retains a one-to-one correspondence between neurons in the original model and their analog counterparts. Our design employs a emph{single} input source for all first-layer weights, a emph{single} resistor per weight, and a bidirectional amplifier for the rest of the layers' weight to handle negative connections without duplicating neurons. We validate our design on a binary XOR classification task over SI{100}{} training epochs and SI{100}{} randomized initializations. Our textbf{single-resistor} approach achieved an average final error of SI{-6.6}{dB} and required approximately SI{568}{} minutes of total CPU time. In comparison, the textbf{doubled-node} design reached SI{-4.6}{dB} error and consumed around SI{1104}{} minutes of CPU time. This equates to nearly 49% less computation for the single-resistor circuit while preserving the standard gradient update procedure—demonstrating that negative weights can be realized more efficiently without doubling input/output neurons.

Keywords: Hardware Security, Physical Design, Test, Verifications, Processor and Memory Design and Architectures
Abstract: Due to intrinsic variations in process conditions and geometrical imperfections, all CMOS devices exhibit statistical distributions in their characteristics. These unwanted variations, which translate to features unique to a given process, fab facility, and device operation, cannot be imitated. But they can be leveraged to enhance hardware security at the chip level. In particular, total harmonic distortion (THD) or linearity performance of a CMOS inverter can be harnessed to identify a process and produce a physically unclonable function (PUF) that is inherently impacted by both material quality and specific operation modes of MOSFET pair used for its construction. In this work, we illustrate how this can be accomplished using integral function method (IFM) that integrates the CMOS inverter response to a simple quasistatic sweep to capture its linearity response without demanding AC measurements. Thanks to its relative simplicity and ease of implementation, this technique can efficiently identify a given process or device family. Consequently, it can lead to the construction of a novel PUF, which employs the resulting statistical distribution of THD to produce random bitstreams as unique regenerative keys for authentication. The number of challenge-response pairs of the proposed PUF can be extremely large as it can leverage three digital-to-analog converters (DAC) to set quasistatic sweep parameters and linearity response thresholds. Therefore, we argue that a CMOS inverter's linearity/distortion performance can become a very valuable marker to enhance root-of-trust in hardware security, avoid counterfeiting, and monitor chip reliability.

Keywords: Hardware Security, Digital Integrated Circuits
Abstract: This work introduces a hybrid random number generator (HRNG) combining true and pseudo-random sources to improve randomness thus security, lower overhead, and enhance scalability. The design incorporates Ring Oscillators to generate true random seeds for fibonacci Linear feedback shift register (LFSR). It is tested with NIST, Diehard, and other suites to ensure statistical validity passing 96.8% passing rate among all tests indicating high randomness. Finally, it is synthesized using multiple technology nodes to analyze area, power, and frequency trade-offs. The proposed method requiring 45 (sq. microns) for 14 nm technology node.

Keywords: Hardware Security, Digital Integrated Circuits, Other Digital Circuits and Systems
Abstract: Electromagnetic side-channel analysis (EM-SCA)-based attacks can efficiently extract encryption keys without direct contact with the hardware running the encryption engine. While architectural and software-based countermeasures have recently been explored, circuit-level design and layout techniques for mitigating EM-SCA at its source remain relatively underexplored. This work inctroduces LEnS: a ul{L}arge language model (LLM)-assisted automatic layout of ul{En}cryption engines for ul{S}ecurity against EM-SCA. We first analyze the impact of EM-dipole-compensated standard cell layouts on EM-SCA resilience. Then, we explore the use of LLMs to automate the generation of standard cell designs with inherent EM-dipole compensation. Through 3D finite element method (FEM) simulations using the ANSYS HFSS tool, we observe that cell-level EM-dipole compensation results in up to approx 4000times reduction of the EM leakage. Extending the cell-level 3D FEM simulations to an AES S-box layout, we demonstrate that the lekage reduction properties hold true, due to the cancellation in the H-field leakage at the transistor-level. The process incurs negligible area and power overhead of <5% for the same performance.

Keywords: Hardware Security, Other Digital Circuits and Systems
Abstract: Ring-Oscillator Based Physical Unclonable Functions (ROPUFs) offer a solution to hardware security problems, but are still vulnerable to machine learning (ML) attacks due to their small sets of Challenge-Response Pairs (CRPs.) To disrupt these attacks, we propose a Moving Target Defense approach by introducing the concept of a minimally shifted layout, introducing unpredictability in the learned CRP set. This approach keeps the ML model from recognizing the patterns that make the ROPUF vulnerable. Our implementation on an Altera DE10Lite FPGA shows that by changing the ROPUF layout, we significantly diminish the effectiveness of the ML attack, dropping the accuracy of the model from 79.63% to 50.57%.

Keywords: Digital Integrated Circuits, Hardware Security, Other Digital Circuits and Systems
Abstract: CRYSTALS-Dilithium (Dilithium), a digital signature scheme based on lattice cryptography, has recently been designated as a standard for post-quantum digital signatures by the National Institute of Standards and Technology. Known for its strong security guarantees and efficient use of polynomial arithmetic, Dilithium offers a promising foundation for future-proof digital signatures. However, implementing such lattice-based schemes in hardware introduces significant challenges due to the high computational demands and structural complexity of their core operations. To overcome these issues, this work focuses on optimizing Dilithium for field-programmable gate arrays (FPGAs), which offer substantial potential for performance gains through parallelism and customized architectural design. We introduce a novel hardware design that improves performance and area by employing a 2×2 butterfly number-theoretic transform capable of computing two transform stages per cycle, along with a conflict-free memory subsystem that leverages pipelined coefficient rearrangement and an address resolution mechanism to ensure continuous data access. Evaluation on an Xilinx Versal Premium FPGA shows that our design enhanced resource utilization and performance, reaching 328 MHz and an area-time product of 5.4 KLUTs × ms at security level 2.

Keywords: System on a Chip (SOC) and Network on a Chip (NOC), Hardware Security, Sensor Interface Circuits and Microsystems
Abstract: Thermal Trojan attacks present a pressing concern for the security and reliability of System-on-Chips (SoCs), especially in mobile applications. The situation becomes more complicated when such attacks are more evasive and operate sporadically to stay hidden from detection mechanisms. In this paper, we introduce Intermittent Thermal Trojans (iThermTroj) that exploit the chips' thermal information in a random time-triggered manner. According to our experiments, iThermTroj attack can easily bypass available threshold-based thermal Trojan detection solutions. Furthermore, we investigate the vulnerabilities inherent to SoCs against thermal Trojans through an in-depth exploration of various Trojan activation and duration scenarios. We also propose a set of tiny Machine Learning classifiers for run-time anomaly detection to protect SoCs against such intermittent thermal Trojan attacks. Compared to existing thermal Trojan detection methods, our approach improves the attack detection rate by 29.4%, 17.2%, and 14.3% in scenarios where iThermTroj manipulates up to 80%, 60%, and 40% of SoC's thermal data, respectively. Additionally, our method increases the full protection resolution to 0.8 degrees Celsius, meaning that any temperature manipulations exceeding 0.8 degrees will be detected with 100% accuracy.

Keywords: Analog Circuits and Systems, 5G & 6G Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: Beam squint presents a significant challenge in high-fractional-bandwidth phased array systems. Conventional approaches typically employ True-Time-Delay (TTD) circuits in fully analog architectures; however, wideband programmable TTD implementations are complex and power-intensive. This work proposes a fully analog transmit front end to mitigate beam squint without using TTD. The architecture utilizes multiple Digital-to-Analog Converters (DACs), each driven by delayed clock signals generated through an ultra-low jitter Phase Interpolator (PI). The phase alignment across the operating bandwidth reduces the beam squint. The proposed system is demonstrated on a 96-element antenna array with 8 DACs, supporting a 10 GHz bandwidth at a 64 GHz carrier frequency.

Keywords: Other Analog/RF Circuits and Systems, Hardware Security, Information Theory, Coding and Security
Abstract: The increasing integration of high-speed wireline networks in cyber-physical systems has raised critical security concerns, particularly regarding unauthorized access and control of safety-critical functionality. This work investigates physical layer authentication techniques that leverage intrinsic channel characteristics for secure, physically and spatially unique communication in high-speed broadcast networks. Specifically, we explore jitter-based fingerprinting and channel cursor adaptation as viable authentication mechanisms. Both techniques are evaluated in terms of their practicality for real-time implementation, distinguishability, and robustness to environmental variations. Simulation results demonstrate that jitter-based authentication provides overall superior uniqueness, with high distinguishability at high losses, whereas cursor adaptation performs better at low losses. The complementary nature of these approaches suggests potential benefits in their dual application in a multi-metric authentication framework

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Other Analog/RF Circuits and Systems, Other AI and Edge Topics
Abstract: An automated design methodology for RF circuits using a feedforward neural network is presented in this paper. Machine learning techniques for circuit design automation require a large amount of data for training. Generation of such large dataset from RF circuit simulation is very time consuming and computationally expensive. The proposed technique uses transfer learning in a two step approach which significantly reduces the amount of data needed from SPICE level circuit simulations. A large dataset, generated from the analytical models, is used in the initial training and a much smaller dataset, generated from the SPICE simulations, is used for transfer learning. The proposed technique is demonstrated through automated design of RF oscillators and very high accuracy is obtained in achieving the target specifications.

Keywords: RF Front-End Circuits, Other Analog/RF Circuits and Systems, 5G & 6G Circuits and Systems
Abstract: This paper presents an implementation of a wideband vector modulator (VM) using two-stage transformer-based IQ generator followed by I/Q Variable-Gain Amplifiers (VGAs). The VGAs are based on Gilbert cell architecture to facilitate wideband output matching due to its relatively small output capacitance, however, the current density variation causes high gain and phase errors. A novel technique is proposed to fix input and output impedances across phase states, minimizing gain and phase errors at the expense of higher power dissipation. The VM is implemented in GF45RFSOI technology and it achieves a peak gain of -1.3dB, covering a 3dB-BW of 24.5 to 40.5 GHz. The simulated RMS gain and phase errors are below 1.20 and 0.3dB, and the total VM core area is 350μmx520μm.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, RF Front-End Circuits, Other Analog/RF Circuits and Systems
Abstract: A low power and wide band frequency divider that can be integrated with W-Band transceiver is pivotal for high speed wireless communication. In this work, a novel class of dynamic latch frequency divider utilizing load modulation is explored. These latches represent an advancement of traditional static current-mode logic (CML) latches, with the regenerative cross-coupled pair eliminated to minimize parasitic effects at the output nodes, thereby achieving maximum speed. Additionally, the input clock modulates the loads to ensure optimal charge retention during hold times. The operation principle and design methodology to determine the maximum and minimum operation frequency is reported. The topology is fabricated in Globalfoundries 22nm FDSOI technology. The divider demonstrates a tunable operating frequency range from 75 to 110 GHz while consuming maximum 7.5 mW DC power from 0.8V supply.

Keywords: RF Front-End Circuits, Mixed-Signal RF and Baseline Circuits, Analog Circuits and Systems
Abstract: This paper introduces an innovative harmonic rejection mixer (HRM) architecture featuring stacked PMOS and NMOS Gilbert-cell stages. The proposed HRM offers optimized harmonic suppression and linearity across the desired bandwidth, while reducing power consumption and enhancing conversion gain compared to conventional HRMs. The NMOS stage is driven by a customized three-level differential signal, generated from two LO signals at 0° and 90° phases using a switched-capacitor circuit. The stacked PMOS stage is driven by a differential LO signal at 135° and 315°, with its current being supplied directly from the NMOS stage. This design reduces power consumption by minimizing the current drawn from the supply and increases conversion gain by allowing a higher load resistance. Linearity is also improved by using two auxiliary NMOS and PMOS transistors biased in the subthreshold region. Their gain expansion cancels out the gain compression of other transistors in the stacked Gilbert-cell stage. The circuit, designed in a 180-nm CMOS process, operates from 315 MHz to 915 MHz, which is suitable for the internet of things (IoT) applications. Based on the post-layout simulation results, the proposed HRM provides a conversion gain of 13–9.25 dB within 315 MHz to 915 MHz while consuming only 524 µW. The third-order harmonic rejection ratio (HRR3) is 39 dB at 700 MHz.