Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Internet of Things (IoT) Theory and Systems
Abstract: High-quality factor crystal oscillator circuits are characterized by prolonged startup times, leading to increased average power consumption in duty-cycled systems. Although injecting energy into the crystal for a precisely determined duration can markedly reduce startup time, this method necessitates an auxiliary injection signal with a frequency within ±6000 ppm of the crystal’s resonant frequency. Generating such a signal typically requires per-chip calibration of the auxiliary source, a process that is both costly and impractical. This work addresses this issue by proposing a self-calibration technique that obviates the need for external calibration. The proposed approach uses the ringing current response of the crystal (which is produced due to a voltage step) to automatically calibrate the injection source. It employs a delay-matching circuit to match the delay of a delay-line to the period of the crystal’s ringing response. Once the delay is matched, the delay-line is reconfigured into a ring oscillator, which produces the requisite injection signal to energize the crystal and facilitate rapid startup. This selfcalibration method offers a cost-effective and efficient solution for minimizing the startup time of crystal oscillators in dutycycled systems. The proposed technique achieves a startup time of 124 cycles and consumes 124nJ of startup energy for a 10 MHz oscillator.

Keywords: Mixed-Signal RF and Baseline Circuits, VCO’s and Frequency Multipliers, PLL’s and Synthesizers
Abstract: This work presents a fast-hopping digital phase-locked loop (DPLL) which could adaptively compensate for the severe supply droop in a large SoC system. Besides the self-stimulus LMS algorithm to capture the optimized gain for two-point injection, a simple solution to remove frequency overshooting due to the ripple pole inside digitally controlled oscillator has been proposed and verified. Bit-shift based digital multipliers are used in LMS and frequency hopping control which speed up operation and cost much less hardware. Simulated in TSMC 2nm process, the proposed DPLL synthesized a nominal 6GHz clock with a reference of 100MHz. When local supply droop is detected, it could hop to a lower frequency mitigating the timing pressure and could recover within 30 reference cycles once supply comes back to normal. The prototype chip consumes 7.5mW@0.65V and achieves the cycle jitter of 132fs-rms

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers
Abstract: This paper proposes a 10-phase dual-path voltage-controlled ring oscillator (VCRO) in 12nm FinFET technology. The extra coupling paths ensure even-phase outputs with improved speed compared to the single-path VCRO. In addition, extended headroom of current source transistor enhances the tuning range and oscillation frequency simultaneously. Moreover, the structural advantage and delay cell's strength are explored to achieve a nominal oscillation frequency of 12.5GHz and a wide frequency tuning range up to 102% with unique even-numbered 10-phase outputs. Comparison between the proposed dual-path VCRO and commonly-used pseudo-differential VCRO is also presented, demonstrating that the proposed dual-path VCRO attains an over 28% wider frequency tuning range with a higher maximum achievable oscillation frequency. Post-layout simulations show that the proposed VCRO covers 8.7GHz to 16.6GHz across PVT variations and exhibits robust performance with a phase noise of -76.5dBc at 1MHz offset frequency when operating at 12.5GHz under a 1V supply voltage.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Digital Integrated Circuits, Linear and Non-linear Analog Systems
Abstract: Accurate modeling of Digitally Controlled Ring Oscillators (DCROs) is crucial for optimizing their performance in Phase-Locked Loops (PLLs) and other high-speed applications. This paper presents a systematic approach to model the frequency and power characteristics of Resistively Decoupled Unit Cell (RDUC)-based DCROs, using an Elmore delay model with nonlinear characterization of RDUC delays. The proposed method efficiently characterizes key parameters, enabling DCRO design automation. Additionally, the RDUC architecture improves radiation hardness, making it ideal for harsh environment applications. This computationally efficient approach enables rapid simulation, significantly reducing design time. The model’s accuracy is validated through experimental results on a 65nm CMOS test chip.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Mixed-Signal RF and Baseline Circuits, Analog Circuits and Systems
Abstract: This work presents a stochastic LC-VCO amplitude peak detector which is non-sensitive to process and device mismatch. A time-interleaving operation of N small detector slices helps to reduce the extra capacitive load of LC tank, mitigating the oscillator frequency degradation. Meanwhile the average output of those detectors can effectively improve the active and passive device mismatch impact by a factor of √N compared to using a single same-size detector. In addition, a neighbor grouping method is adopted in the averaging circuits to save half the number of sampling capacitors. Simulated in TSMC 3nm process, for which 0.96V is the maximum tolerant voltage for thin FinFETs, this work can narrow down the clamp range within ±2.5mV to guarantee an LC-VCO peak-to-peak amplitude of 0.94V~0.96V over process corners.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Analog Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: This paper presents a dual-loop reference-less Clock and Data Recovery (CDR) architecture implemented in TSMC 28nm CMOS technology for PCIe Gen3 applications. The proposed design features an extended BiDirectional Frequency Detector (BFD) that enables rapid frequency acquisition in both directions over a wide locking range. By utilizing DNFAST and DNSLOW signals, the BFD dynamically adjusts the correction rate based on frequency error, ensuring accurate frequency tracking and a seamless transition from frequency acquisition to phase tracking. This approach significantly enhances the locking performance and stability of the CDR system. The proposed CDR achieves a locking time of 4.1 μs when transitioning from PCIe Gen1 (2.5 Gbps) to PCIe Gen3 (8 Gbps) under a PRBS7 pattern with a power consumption of 3.9mW at 0.9V power supply.

Keywords: AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neural Learning Circuits & Systems, Analog, Digital and Mixed Signal Processing
Abstract: The Margin-Propagation (MP) is a paradigm for designing analog computing circuits that, like digital circuits, are scalable across biasing conditions and process nodes. Like digital circuits, MP-based analog circuits and systems are modular and robust to process, voltage, and temperature variations. These features make MP-based analog circuit design amenable to automation and high-level synthesis. This paper proposes such a design framework using factor graphs as the foundational descriptors to specify the interdependency between different analog computational primitives. Using Python scripting language, the proposed framework translates an input factor graph to its equivalent SPICE-compatible circuit netlist that can be used to validate the intended functionality using an MP-based message-passing algorithm. The proposed framework also allows for the integration of design optimization strategies such as precision tuning, variable elimination, and mathematical simplification. We demonstrate the versatility of our framework for tasks such as Bayesian inference, Low-Density Parity Check (LDPC) decoding, and analog Artificial Neural Networks (ANN). Netlist simulation results align closely with software implementations, affirming the efficacy of our proposed automation tool.

Keywords: AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neural Learning Circuits & Systems, Machine Learning at the Edge
Abstract: A mixed-signal hardware accelerator for solving a modern Hopfield network (MHN) is presented. Unlike classical Hopfield networks (CHNs), MHNs offer significantly higher storage capacities while requiring fewer updates to reach a solution. The proposed accelerator integrates digital storage and binary computation with analog current-mode processing to implement the exponential interaction functions essential for the strong nonlinearity characteristic of MHNs. Designed in TSMC 65nm CMOS technology, the network consists of eight 8-bit binary neurons. Circuit simulations across 256 input combinations demonstrate that, when prompted with an input, the eight-neuron network converges to one of eight stored patterns within two asynchronous update cycles, taking 1.08 ms. Of all inputs, 91% are transformed into either the closest or second-closest stored pattern, as measured by Hamming distance. Supplied by a single 1V supply, the accelerator consumes 63.3 µW, which makes it the most power-efficient solution among CHN or CHN-based associative memory hardware accelerators compared. Achieving eight pattern storage using only eight neurons, the proposed accelerator demonstrates the significant efficiency of MHNs in terms of patterns stored per neuron in an energy-efficient manner.

Keywords: AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neuromorphic Circuits and Systems, Analog Circuits and Systems
Abstract: Kolmogorov-Arnold Networks (KANs) offer very interesting and largely unexplored architectural advantages compared to deep perceptron systems for artificial intelligence (AI) systems. This paper shows that analog KANs can be efficiently implemented in standard CMOS technology by using multi-input multi-transistor amplifiers to compute analog dot products. Simulation results in a 65nm CMOS process suggest that such KANs can provide comparable accuracy to multi-layer perceptrons (MLPs) while using fewer transistors per computation.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Secure AI Hardware, Hardware Security
Abstract: Existing defenses that deploy encryption add significant overheads, that are unacceptable for resource-constrained edge neural processing units (NPUs). We make two significant observations in the context of quantized inference on NPUs: (a) requantisation causes significant rounding errors, leading to significant drop in the first layer extraction rate, making it impossible to extract the deeper layers; and (2) the restricted sweep range due to requantisation and the non-linearty caused by max-pooling, together make the Q-point search impossible for some weights. Empirical evaluation on a wide range of unencrypted 8-bit quantized neural network architectures upto 243 layers, demonstrated an average Top-1 RE accuracy of 7.6% and 0.1%, respectively. We believe these results will be very helpful for chip designers to avoid encryption altogether and improve performance, power, and area (PPA) metrics without comprimising side-channel resilience.

Keywords: Machine Learning at the Edge, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: This paper proposes a novel method for estimating the remaining useful life (RUL) of aircraft engines using the widely recognized dataset from the 2008 International Conference on Prognostics and Health Management (PHM’08) challenge. Accurate RUL prediction is essential in industrial settings as it enables proactive maintenance strategies that minimize downtime, reduce inventory costs, and optimize labor efficiency. This work presents an innovative artificial intelligence (AI)-on-chip solution based on reservoir computing, specifically designed for efficient RUL estimation. The proposed solution achieves an average R2 score of 0.94 across 100 engines in the software model, demonstrating its effectiveness in capturing complex degradation patterns. Additionally, a test-chip fabricated in 28nm CMOS process achieves an average R2 score of 0.84. By combining reservoir computing with an efficient hardware design, this approach offers a promising path toward low-power, high-accuracy RUL prediction systems that can be deployed directly on-chip.

Keywords: Other Digital Circuits and Systems, Digital Integrated Circuits, Machine Learning at the Edge
Abstract: This paper investigates the potential of approximate addition for k-means clustering which is a popular unsupervised machine learning technique. The k-means clustering aims to organize data into k clusters, where k represents the number of centroids that are the clusters’ centers. During clustering, data points are assigned to the nearest centroid by minimizing the within-cluster sum of squares (WCSS). A lower WCSS value indicates better clustering. Typically, WCSS is computed with high precision using an accurate adder. In this paper, we compute WCSS for clustering using various approximate adders and compare the results with those obtained using the accurate adder. We also introduce a new approximate adder that yields WCSS values identical to or closer to those calculated using the accurate adder. We performed k-means clustering of three open-source artificial datasets with different complexity using accurate and approximate adders. The clustering results obtained validate the efficiency of the proposed approximate adder. Hardware implementations of accurate and approximate adders using a 28nm CMOS standard cell library show that the proposed approximate adder achieves a 26% reduction in delay, a 21% reduction in area, and a 22% reduction in power compared to the accurate adder. The new approximate adder also outperforms several other approximate adders in terms of the design metrics while ensuring good clustering quality.

Keywords: Other Beyond CMOS Topics, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: The inherent functional behavior of reconfigurable field effect transistors (RFETs) is applied to different topologies of operational amplifiers. This leads to op-amps with unique abilities. By switching the internal bias voltages, the proposed op-amps can still perform even if the supply voltage is inverted. Furthermore, we demonstrate that the tunability of RFETs allows for parameter adjustment at runtime. In that manner, the op-amp can be optimized for specific performance characteristics, such as higher DC-gain or GBW. The developed floating biasing circuit for the differential pair based on RFETs enables utilization of the full reconfigurability that would not be possible with regular CMOS devices.

Keywords: Other Beyond CMOS Topics
Abstract: This paper presents a novel pixel readout circuit designed for a 0.56um pixel pitch CMOS image sensor, with back-end-of-line (BEOL)-compatible amorphous oxide semiconductor channel transistors. By monolithically stacking W-doped In2O3 (IWO) transistors onto two BEOL tiers above each photodiode, the proposed voltage-domain global shutter architecture preserves transistor area for improved noise performance without increasing the complexity associated with additional wafer stacking. Measured low-frequency (1/f) noise characteristics of the IWO transistor reveal a Hooge’s parameter 4.98x10^(-3) comparable to conventional silicon MOSFETs with high-k gate dielectrics. Noise analysis and circuit simulation results demonstrate a read noise of 1.81 electrons and a dynamic range of 70.4dB, highlighting the potential of BEOL-stacked oxide semiconductor devices for next-generation submicron CMOS image sensors.

Keywords: Analog Circuits and Systems, MEMS/NEMS and Nano-Electronics, VCO’s and Frequency Multipliers, PLL’s and Synthesizers
Abstract: Phase noise is a key factor affecting the short- term stability of clocks, specifically for low power designs. To address the need for low-cost, low-SWaP (size, weight, and power) micro-electromechanical system (MEMS)-based clocks in wearable/military applications while enhancing short-term stability, we present a 4.33 mW, 64.5 MHz tunable-gain multi- stage trans-impedance amplifier (TIA)-based oscillator in 65nm CMOS. Integrated within a closed-loop system with a piezoelec- trically transduced shear-BAW resonator, the proposed CMOS TIA design achieves phase noise of -118.2 dBc/Hz @ 1KHz offset frequency, a noise floor of -158.2 dBc/Hz, 205.1dB FOM @ 1KHz offset, and an exceptional fres X Q product exceeding 10^14, demonstrating significant performance improvements in short-term stability of CMOS-MEMS oscillators.

Keywords: Digital Integrated Circuits, Quantum Hardware Systems, AI Digital Hardware, Accelerators, and Circuits
Abstract: Digital processing implemented in a technology optimized for reduced temperatures, such as 77K, has significantly improved power dissipation. Operating at cryogenic temperatures benefits both active devices and the properties of passive elements, such as interconnects. With over 30% gate delay and power dependent on interconnect, this paper focuses on optimizing on-chip metal interconnects based on a design technology co-optimization (DTCO) methodology for cryogenic environments. By refining the metal stack architecture, we achieve substantial improvements, yielding power savings of >10% for synthesized logic and >80% for repeaters at 77K. The results are validated in 14-nm-class FinFET technology.

Keywords: Analog Circuits and Systems, Hardware Security, Other Sensory Circuits and Systems
Abstract: Random number generators that utilize arrays of entropy source elements suffer from bias variation (BV). Despite the availability of efficient debiasing algorithms, optimized implementations of hardware friendly options depend on the bit bias in the raw bit streams and cannot accommodate a wide BV. In this work, we present a 64 × 64 array of perimeter gated single photon avalanche diodes (pgSPADs), fabricated in a 0.35 µm standard CMOS technology, as a source of entropy to generate random binary strings with a BV compensation technique. By applying proper gate voltages based on the devices’ native dark count rates, we demonstrate less than 1% BV for a raw-bit generation rate of 2 kHz/pixel at room temperature. The raw bits were debiased using the classical iterative Von Neumann’s algorithm and the debiased bits were found to pass all of the 16 tests from NIST’s Statistical Test Suite.

Keywords: Power Management of Electric Vehicles, Wireless Charging and Energy Harvesting, Smart Power Management for High-Performance Cloud and AI Data Centers
Abstract: This study presents the fabrication and experimental analysis of interdigitated supercapacitors through the utilization of a screen printing technique. The proposed device features an interdigitated structure with a primary graphene electrode and a secondary layer of silver paste, employing a H_3PO_4/PVA gel electrolyte as the dielectric medium. Furthermore, CV analyses at different sweep rates highlighted the versatility of the fabricated supercapacitors. In order to further validate the design and performance features, simulations were run to assess the electrode potential under an external bias. The integration of graphene and silver paste layers, along with the efficient screen printing technique, make this research a promising step toward advancements in energy storage applications.

Keywords: Wireless Charging and Energy Harvesting, Regulators, References and Reliability Methods, Analog Circuits and Systems
Abstract: A 40.68 MHz single-stage 2X/0X reconfigurable resonant regulating (R3) rectifier is proposed for improving the power conversion efficiency (PCE) of a wireless power transfer (WPT) receiver. AC to DC rectification and voltage regulation are achieved in one stage using only two power MOS transistors. AC to DC rectification is realized by a full-wave rectifier with an embedded voltage-doubler consisting of only two active diodes, with one using a PMOS and the other an NMOS power transistor. Turn-on delay, reverse current, and multiple-pulsing are eliminated using low-power digital techniques. Mode-switching for voltage regulation is realized through pulse width modulation (PWM) control, and Type-II compensation is used to achieve fast transient response. The proposed design is implemented with a 0.13 µm CMOS process. The output voltage is regulated at 1.2 V. The measured PCE of the single-stage receiver reaches 90.7%. The measured undershoot and overshoot are lower than 95 mV, and the settling time is less than 25 μs when the load switches between 1.2 mA and 12 mA.

Keywords: Other Power Circuits and Systems
Abstract: High-efficiency boost converter IC is proposed for Silicon Photomultiplier (SiPM) applications, addressing the challenges of low efficiency and slow transient response in conventional designs. The proposed converter operates with an input voltage range of 3.3V to 5V and provides a stable output voltage up to 30V, supporting a load current of up to 10mA. Conventional boost converters suffer from high switching losses under light-load conditions, leading to reduced efficiency and limited loop bandwidth (BW), which results in slow transient response. To overcome these limitations, the proposed boost converter incorporates a pulse-skipped switching scheme, which significantly reduces switching losses under light-load conditions, improving overall efficiency. Additionally, a Gm-boosted compensator is introduced to enhance loop BW, ensuring faster transient response and improved output stability. The boost converter is implemented in a 250 nm BCD process, which allows for high-voltage operation while maintaining integration flexibility. Simulation results demonstrate that the proposed design achieves an efficiency improvement up to 86.3% at a 1mA load, while the loop BW is increased by 14 times compared to conventional designs. These enhancements make the proposed boost converter well-suited for long-duration SiPM-based radiation detection systems that require high efficiency and fast response.

Keywords: Wireless Charging and Energy Harvesting, Analog Circuits and Systems
Abstract: We propose a power management strategy that maximizes the power harvested from a triboelectric nanogenerator using a Parallel Synchronous Switched Harvesting on Inductor (P-SSHI)-based rectifier. By analyzing the charge transfer from the rectifier to the DC-DC converter, we observe increase in the extracted power by limiting the rectifier capacitor discharging. We design and implement a power management system based on the proposed switching technique. The technique is suitable for integration into a power management system of smart self-powered sensors, such as those used in smart knee implants following total knee replacement (TKR) surgery. We demonstrate 37% increase in the harvested power at the TENG interface compared to the conventional switching in P-SSHI-based rectifier.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Sensor Interface Circuits and Microsystems
Abstract: This paper discusses an integrated negative bias voltage generator (NVG) for large-area monolithic active pixel sensors (MAPS). The circuit, which is implemented in a 110 nm partially-depleted silicon-on-insulator (PDSOI) process, uses a frequency-controlled charge pump to generate a programmable voltage between -1 V and -5 V. Simulations show that the output voltage has an error <3% over the entire range, ripple <640 uVpp for a 1 nF load, and excellent line and load regulation.

Keywords: Analog Circuits and Systems, Other Power Circuits and Systems
Abstract: This paper describes an analytic method to determine the optimal load capacitance of a full wave rectifier (FWR) in triboelectric energy harvesters. The amount of average power delivered from the harvester to the rectifier grows in each cycle, eventually reaching a peak value. In steady state, the average rectifier power depends on the harvester characteristics and the load capacitance of the rectifier. For a given harvester, if the load capacitance is too small, the rectifier power does not reach the maximum power in steady state. Alternatively, if the load capacitance is too large, the number of cycles to reach maximum power increases, causing additional delay. An analytic method is proposed to estimate the optimum value of this capacitance, which ensures maximum power while minimizing the transient time. The results are validated with the measurement results of a triboelectric harvester.

Keywords: Other Areas in Biomedical Circuits and Systems, Analog Circuits and Systems, Integrated Biomedical Systems
Abstract: This paper presents a resonant driver with energy-recycling capability for battery-powered, high-voltage (HV), portable ultrasound (US) systems, where minimizing power consumption is crucial. The proposed HV driver significantly reduces power loss by utilizing a capacitor matched to the transducer’s capacitance and a small off-chip inductor to recycle energy, which is typically wasted in conventional class-D designs. Additionally, an on-chip calibration mechanism compensates for capacitor mismatches, further optimizing power efficiency. The theoretical analysis of the proposed energy-recycling technique is also provided. The proposed driver can efficiently drive large capacitive loads, particularly those inherent in piezoelectric micromachined US transducers (PMUTs). The circuit is designed and simulated in TSMC 0.18-µm HV BCD technology, driving a 1 nF load at 2 MHz with 30 V pulses, achieving 80.1% reduction in power consumption compared to conventional class-D pulsers.

Keywords: Secure AI Hardware, Information Theory, Coding and Security
Abstract: Modern computing systems face security threats, including memory corruption attacks, speculative execution vulnerabilities, and control-flow hijacking. Although existing solutions address these threats individually, they frequently introduce performance overhead and leave security gaps. This paper presents a Variable Record Table (VRT) with a unified hardware-assisted framework that simultaneously enforces spatial memory safety against buffer overflows, back-edge control-flow integrity (CFI), and speculative execution attack detection. The VRT dynamically constructs a protection table by instrumenting runtime instructions to extract memory addresses, bounds metadata, and control-flow signatures. Our evaluation across MiBench and SPEC benchmarks shows that VRT successfully detects all attack variants tested with zero additional instruction overhead. Furthermore, it maintains memory requirements below 25KB (for 512 entries) and maintains area / power overhead under 8% and 11.65 μW, respectively. By consolidating three essential security mechanisms into a single hardware structure, VRT provides comprehensive protection while minimizing performance impact.

Keywords: Hardware Security, Other AI and Edge Topics, Other Digital Circuits and Systems
Abstract: Ring Oscillator Physical Unclonable Functions (ROPUFs) serve as a promising hardware security primitive; however, their susceptibility to machine learning (ML)-based attacks remains a critical concern. This work investigates the vulnerability of ROPUFs by leveraging knowledge-driven models popularly referred as Large Language Models (LLMs) for data augmentation and training ML classifiers to predict Challenge- Response Pairs (CRPs). We evaluate the performance of algorithms such as Decision Trees (DT), Random Forest (RF), KNearest Neighbors (KNN), Support Vector Machines (SVM), and Gradient Boosting (GB) under two scenarios: (1) assuming the adversary has access to 5% of the CRP data the models are trained and tested on 3,000 real CRPs, and (2) models trained on 15,000. augmented CRPs and tested on the 3,000 real CRPs. The results demonstrate that with only 3,000 legitimate CRPs, for the selected five algorithms, RF achieved 61.67%, followed by SVM (60.83%), KNN (58.33%), DT (57.33%), and GB (57.33%). However, when augmenting the dataset to 15,000 CRPs, Random Forest improved to 68.6%, DT to 66.53%, KNN to 67.00%, SVM to 66.30%, and GB to 61.03%, demonstrating significant performance gains. These findings highlight the efficacy of LLM-based data augmentation in enhancing attack success rates on ROPUFs, reinforcing the need for improved security mechanisms against ML-based adversaries.

Keywords: Hardware Security, Other AI and Edge Topics
Abstract: Hardware Trojan (HT) detection in integrated circuits including Field Programmable Gate Arrays (FPGAs) faces significant challenges due to the scarcity and imbalance of high- quality side channel datasets. This paper addresses the above-mentioned challenge by employing Conditional Wasserstein Generative Adversarial Networks (CWGANs) to generate synthetic side channel traces, specifically power signals, under both Trojan infected and Trojan free circuit conditions. The generated synthetic signals not only replicate real world side channel characteristics but also support scalable and cost-effective model training. A Random Forest (RF) classifier trained on original power dataset achieves 93% accuracy, validating its effectiveness. When trained and tested solely on synthetic data, the models exhibit near perfect accuracy, confirming the realism and utility of the generated samples. However, evaluations reveal a domain shift when synthetic trained models are applied to real data, resulting in a reduced accuracy of 83.62%. To address this domain shift, we implement Domain-Adversarial Neural Network (DANN) adaptation techniques, which significantly improve cross-domain performance to 92.87%, nearly matching the baseline accuracy. These findings highlight the importance of generative models in hardware security and provide practical options for bridging the synthetic-to-real performance gap using advanced domain adaption techniques.

Keywords: AI-IoT Systems and Applications, Heterogeneous Integration
Abstract: The growing reliance on semiconductor-based technologies in the automotive sector has intensified the demand for a highly skilled and industry-ready workforce in the United States. To address this need, Wayne State University’s Electrical and Computer Engineering Department has developed a series of free, stackable hybrid workshops focused on semiconductor engineering, circuit design, power electronics, and printed-circuit-board technologies. Designed to bridge the gap between traditional academic education and evolving industry requirements, these workshop series integrate virtual instruction with hands-on, in-person laboratory sessions, providing participants with practical expertise applicable to real-world semiconductor applications. To assess educational impact, pre- and post-workshop surveys are administered that measure knowledge gains, skill development, and confidence in applying newly acquired competencies. These training modules represent a strategic model for advancing semiconductor workforce development, supporting national efforts to enhance domestic manufacturing capacity, technological leadership, and economic resilience.

Keywords: Other Beyond CMOS Topics
Abstract: The Lurie Nanofabrication Facility (LNF) is a shared research facility of the University of Michigan’s College of Engineering. Our mission is to serve technology educators and creators through broad access to advanced nanofabrication equipment and staff expertise in a safe, collaborative environment. In addition to facilitating world-class research, the LNF also provides training and education for undergraduates, high school students, and members of the community to garner interest in working in the semiconductor field. The LNF achieves this by relying on its staff and members of the user community.

Keywords: AI-IoT Systems and Applications
Abstract: This study explores the use of 360-degree Virtual Reality (VR) technology to enhance semiconductor training, focusing on cleanroom procedures, equipment handling, and safety protocols. By immersing trainees in realistic, interactive environments, 360 VR offers an accessible and scalable alternative to traditional hands-on training, particularly in highly controlled or hazardous settings. The project investigates the effectiveness of VR experiences in improving knowledge retention, procedural accuracy, and learner engagement, and identifies opportunities and limitations for integrating 360° VR into semiconductor workforce development programs.

Keywords: System on a Chip (SOC) and Network on a Chip (NOC), Hardware Security, Analog, Digital and Mixed Signal Processing
Abstract: The development of increased semiconductor manufacturing to reduce supply chain dependencies in many nations has led to enhancing workforce development education in those countries. In addition to the increase at individual universities and colleges, several education institution consortiums have been developed. This paper describes some of those consortiums in the USA, and specific supply chain developments for very long life-cycle systems, where the life-cycle can be around 40 years. Some of these developments are specific to analog designs using methods of analog time encoding.

Keywords: Digital Integrated Circuits, Power Management of Electric Vehicles, Other Sensory Circuits and Systems
Abstract: This paper describes a four-part workforce training curriculum designed for southeast Michigan’s needs for technical expertise in semiconductors, electric vehicles, and mobility. Developed for the state of Michigan’s Economic Development Corporation (MEDC), this program seeks to train both students and working professionals in 4 topical areas: 1) Power electronics and EV motors; 2) Printed circuit board (PCB) design and manufacturing; 3) Semiconductor chip design; and 4) Semiconductors and sensors for automotive applications. This paper describes the overall structure of the program and the details of each area. The curriculum is expected to be deployed in the 2025-2026 academic year.

Keywords: RF Front-End Circuits, 5G & 6G Circuits and Systems
Abstract: This work presents a highly linear, multi-function 21–26 GHz (K-band) power amplifier (PA) / mixer implemented in GlobalFoundries' 22nm FD-SOI process. The PA also operates as an up-conversion mixer by utilizing the back gate as an IF input. The design features a differential stacked topology with twelve NFET transistors, leveraging the back gate for biasing and mixing. With a positive back-gate bias, the PA achieves a 12.7 dB gain, 22.3 dBm output power, and 13% PAE at 22 GHz. In mixer mode, it achieves a –17.6 dB conversion gain for a 0.3 GHz IF signal. The circuit exhibits excellent linearity, delivering 15.2 dBm and 13.7 dBm output powers for 400 MHz 64-QAM and 256-QAM signals, respectively, with EVM better than –26.2 dB and –29.4 dB. These results demonstrate the circuit’s potential for high-data-rate and spectrally efficient communication systems.

Keywords: RF Front-End Circuits, 5G & 6G Circuits and Systems, Wireless Mobile Circuits and Systems and Connectivity
Abstract: This paper presents a highly compact 28 GHz power amplifier (PA) designed in 22-nm fully-depleted silicon-on-insulator (FDSOI) for mm-Wave 5G wireless application. The proposed PA utilizes an innovative and efficient transformer-based output matching network (OMN) with high transformation ratio to boost the saturated output power (P_sat) without using bulky power combining network, for compactness and efficiency. Detailed electromagnetic (EM) simulation was performed to create a low-loss 1-2 transformer with a high coupling (k) ~ 0.8 at 28 GHz and self-resonance frequency (SRF) > 50 GHz, with primary and secondary inductances of 175 pH and 857 pH, and quality factor of 14.5 and 10, respectively. Biased in Class-AB, the proposed PA achieves a P_sat of ~24.2 dBm, a power gain of 21 dB and a peak power-added-efficiency (PAE) of 36.5% with a core area of 0.106 〖mm〗^2, occupying significantly smaller area than the state of the art mm-Wave PAs using power combiner to achieve similar P_sat.

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a 12-b, 5-GS/s frontend for a time-interleaved (TI) photonic analog-to-digital converter (PADC) system. The proposed frontend architecture enables an interface between the output of a photodiode to commercial-off-the-shelf (COTS) analog-to-digital converters (ADCs). The frontend incorporates a novel single-ended-to-differential converter (S2D), analog interleaver and output buffer to drive the COTS ADCs. A prototype was fabricated in a 28-nm CMOS process. The measured prototype achieves an SFDR of an average of 54 dB with an analog input spanning 50 MHz to 1 GHz and sampling rate of 5 GS/s. The fabricated prototype occupies an area of 3.63 mm^{2} and consumes 2.57 W of power.

Keywords: Converters, ADC, DAC and others, Mixed-Signal RF and Baseline Circuits, Analog Circuits and Systems
Abstract: This paper presents a 64-way, two-stage track-and-hold (T/H) circuit operating at a sampling rate of 64 GS/s for high-speed time-interleaved analog-to-digital converters (TI-ADCs). To meet the stringent linearity and bandwidth requirements of subsequent ADC stages, a switched push-pull buffer (S-PPB) is proposed, featuring enhanced robustness against clock mismatch and lower distortion. A digitally controlled resistor ladder is employed to provide a tunable common-mode voltage range of 400–600 mV at the output of PPS-PPB, ensuring compatibility with the input common-mode requirements of sub-ADCs. For two-stage sampling, a sampling phase alignment technique effectively compensates for process, voltage, and temperature (PVT)-induced timing variations, preserving signal integrity. The design is implemented in 16-nm FinFET technology, post-layout simulation results demonstrate that at a sampling rate of 64 GS/s, the T/H circuit with over 30 GHz bandwidth achieves signal-to-noise-and-distortion ratios (SNDR) of 46.2 dB and 38.9 dB for 1-GHz and 30-GHz 1-Vppd input signals, respectively, which are sufficient for high-speed 6–8-bit data converters in ADC-based receivers.

Keywords: RF Front-End Circuits, Physical Design, Test, Verifications, Other Analog/RF Circuits and Systems
Abstract: This paper presents the design automation of two Low Noise Amplifier (LNA) topologies - the Noise Cancelling and the Resistive Feedback LNAs. The LNAs were designed using TSMC 28nm technology and optimized for a given set of specifications of Gain ≥ 20 dB, NF ≤ 2dB and IIP3 ≥ − 10 dBm over 1.1 GHz to 1.5 GHz. The algorithm performs PVT corner simulations and sensitivity checks. It is capable of working on any process technology node, and for a wide range of LNA specifications. The runtime of this optimization code is about 300 seconds on an i9 system with 32GB memory.

Keywords: Technologies for Smart Sensors, Physical and Chemical Smart Sensing Systems, Other Sensory Circuits and Systems
Abstract: A novel transducer is presented for measuring low velocities of ocean currents based on the magnetic field. The device employs a tilt-magnetic transducer using the principle of water drag. The inclination of a magnet, caused by the drag force of the water flow, allows us to infer its velocity. Finite element simulations were conducted to evaluate the system behavior. These simulations determined the magnetic forces and established a linear correlation between the angular displacement and the applied force, similar to a mechanical spring. Both experimental and simulation results demonstrate the sensor's high sensitivity and precision. This enables its usage in monitoring marine environmental conditions and assessing the impact of industrial activities on coastal biodiversity.

Keywords: Physical and Chemical Smart Sensing Systems, Other Sensory Circuits and Systems, Analog Circuits and Systems
Abstract: Particle detection at micron and sub-micron scales is critical for a wide range of applications, including environmental monitoring and health assessments. Through the use of high-voltage parallel plate capacitors in a continuously flowing microfluidic channel, we demonstrate a novel method for increasing the particle resolution of capacitive particle sensors. This work presents a parallel plate capacitor sensing architecture that achieves 1-micron resolution with a signal-to-noise ratio of 13 dB using commercially available components. Unlike state-of-the-art interdigitated capacitor-based approaches, our method enables real-time, continuous flow measurements by realizing particle detection with high temporal resolution. These advancements establish the feasibility of parallel plate-based particle detection by providing the first qualitative analysis of a system-wide approach.

Keywords: Analog Circuits and Systems, Wireless Charging and Energy Harvesting, RF Front-End Circuits
Abstract: In this paper, we describe the design and simulation of a battery-free, low power, address-based channel selector for simultaneous selection of one or more electrodes in a medical implant, implemented in the Skywater SKY130 process. The design was simulated for a 4-electrode implant by transmitting a 4-bit address which was processed at the channel selector to enable any combination of channels. The design uses binary pulse width modulation with 100 ns and 8 ns pulse widths, and it features a wakeup delay of 103 µs and a bit rate of 1.67 Mbps. The results discussed herein demonstrate the device's scalability to transmit an 'n' bit channel selection address and use it to activate a specific channel for several biomedical applications like stimulation, sensor readout and actuation.

Keywords: Other Analog/RF Circuits and Systems, Analog Circuits and Systems, Sensor Interface Circuits and Microsystems
Abstract: Battery Energy Storage Systems (BESS) have gained prominence due to an increased focus on renewable energy and the limited availability of fossil fuels. Accurate monitoring of each cell in the BESS is imperative and requires a sensing Analog Front-end (AFE) to maintain the safety and reliability of the BESS. However, state-of-the-art AFE systems can monitor series-connected cells only and need an interconnected management module to monitor the parallel-connected modules. This leads to high system latency, greater power consumption, and increased form factor of the hardware. This article introduces a novel, highly accurate, energy-efficient, and high-speed mixed signal AFE architecture to monitor both series and parallel connected cells simultaneously in the BESS. The AFE architecture based on High Voltage (HV) Subtractors and Analog Multiplexers has been designed using the TSMC 180nm BCD process. The results show a high measurement accuracy of <0.1 mV for cell voltage and current, with an 80% improvement in accuracy over the state-of-the-art AFE systems. The maximum data conversion time is 8μs, and the system is 78.76% faster than the conventional AFE.

Keywords: Biomedical Signal/Image Processing, Other Areas in Biomedical Circuits and Systems, Technologies for Smart Sensors
Abstract: The unique 24 GHz Doppler radar signatures of foraging honeybees were shown to resemble a linear frequency-modulated waveform. A representative signature was used as a reference waveform in a pulse compression process. Pulse compression enabled the selective detection and counting of foraging honeybees with increased sensitivity and temporal selectivity. A modified, complex Pearson correlation process implemented the digital pulse compression. This efficient technique allowed real-time processing on a 600 MHz CPU microcontroller.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, System on a Chip (SOC) and Network on a Chip (NOC)
Abstract: As semiconductor technologies scale down, reliability degradation due to device aging has become a critical challenge, especially in safety-critical applications. Negative Bias Temperature Instability (NBTI) is a dominant aging mechanism in PMOS transistors, leading to threshold voltage shifts and performance degradation over time. This paper presents a robust on-chip sensor that directly monitors BTI-induced threshold voltage shifts using a differential architecture. Our system compares a stressed MOS transistor (the device under test, DUT) with a reference transistor whose effective size is digitally controlled to match the DUT’s drain current. This mixed-signal approach ensures a digital representation of the BTI-induced threshold shift, ensuring rapid measurements essential for capturing degradation before significant NBTI recovery occurs. Using Cadence Spectre/AMS simulations, the sensor has been validated as a reliable monitor for NBTI in MOS devices. Furthermore, measurements of linearity metrics in analog-to- digital converters (ADC) confirm the robustness of the device against process variations and local mismatches.