Keywords: Image, Video and Multi-Dimensional Signal Processing, Signal Processing Theory and Methods, Biomedical Signal/Image Processing
Abstract: Respiratory rate is an important physiological indicator for monitoring livestock health, yet existing approaches typically rely on contact sensors or specialized detectors for anatomical regions, which limits scalability in real farm environments. This paper presents a vision-based framework for non-contact respiratory monitoring of cattle using commodity video streams. The proposed pipeline performs object detection and multi-object tracking to isolate individual animals and extracts motion representations from cropped video regions using pretrained spatiotemporal encoders. These motion features are projected to a compact representation and used to estimate respiratory rate through lightweight regression models. Experimental evaluation on farm-collected videos demonstrates that the system captures respiratory dynamics across animals and recording conditions, demonstrating the feasibility of vision-based respiratory monitoring in unconstrained farm environments. A detailed latency analysis further examines the computational cost of each pipeline component and highlights the trade-offs between motion representations and system throughput. The results suggest that vision-based respiratory monitoring can serve as a practical sensing modality for smart agricultural monitoring systems.

Keywords: Machine Learning at the Edge, Deep Learning for Multimedia, Neural Networks and Fuzzy Logic
Abstract: Since the introduction of computationally efficient hardware for neural networks in the early 2010s, there has been explosive growth in artificial intelligence (AI). When the Transformer was introduced in 2017, it revolutionized many applications, including text-to-speech (TTS) for voice cloning. This paper evaluates the performance of two TTS systems, F5-TTS and E2-TTS, on the NVIDIA® Jetson Orin Nano, a resource-constrained platform. At varying power levels, we compare computational efficiency, word error rate, and speech fidelity, highlighting the advantages and limitations of embedded devices.

Keywords: Neural Learning System Algorithms and Applications, AI-IoT Systems and Applications, Machine Learning at the Edge
Abstract: Edge computing is an increasingly popular method of performing smart device tasks in the age of Internet of Things. As machine learning applications and utility have grown due to the scaling of large models, implementations of small-footprint models at the edge such as keyword spotting models have lagged behind in utility and performance comparatively due to the compute and power-budget constraints of edge devices. This paper proposes a top-k feature selection technique that reduces the computational cost of inference while maintaining all or most performance compared to a base model. The results demonstrate that the proposed approach reduces multiply--accumulate operations by 62.4% while preserving 98.9% keyword recognition accuracy relative to the baseline, making it well suited for low-power edge AI applications.

Keywords: Physical Design, Test, Verifications, Analog Circuits and Systems, Other Analog/RF Circuits and Systems
Abstract: Commercial semiconductor parameter analyzers are costly instruments that restrict access to device characterization in educational laboratories. This study introduces a cost-effective semiconductor parameter analyzer specifically designed for MOSFET testing in both teaching and research settings. The proposed system utilizes a dual-source-measure unit (SMU) architecture, enabling independent control of gate-source and drain-source voltages via digital-to-analog converter (DAC)-driven operational amplifier stages. A microcontroller manages voltage sweeps and collects current and voltage data through integrated sensing circuits. The hardware is constructed on a four-layer mixed-signal printed circuit board (PCB) to minimize noise and enhance measurement stability. Experimental results for MOSFET transfer and output characteristics confirm reliable bias control at an estimated hardware cost of approximately 30.

Keywords: Analog Circuits and Systems, Analog, Digital and Mixed Signal Processing
Abstract: This paper introduces a fully differential, improved sub-volt-supply, offset-compensated switched-capacitor amplifier based on dual-output op-amps. It operates with ±0.45V supplies in 180nm CMOS technology, with a 1.8V nominal supply. The circuit uses a fully differential op-amp with auxiliary and main output stages that do not reset to zero each cycle, unlike conventional switched-capacitor circuits. This provides true sample-and-hold output signals that greatly relax the op-amp’s slew-rate requirements, allowing higher operating speed with reduced power dissipation.

Keywords: Regulators, References and Reliability Methods, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a chopper-stabilized Brokaw bandgap reference for low-noise sensor readout circuits. Chopping of the bandgap amplifier suppresses flicker noise and offset, but introduces ripple at the chopping frequency and its harmonics. To suppress this ripple with small area overhead, a continuous-time (CT), AC-coupled ripple reduction loop (RRL) with an in-loop low-pass filter (LPF) is employed. The RRL suppresses the ripple at the chopping frequency, while the LPF attenuates the residual ripple generated within the RRL at twice the chopping frequency. Measurements on 10 samples over a temperature range from −40 ◦C to 140 ◦C show that the proposed scheme suppresses the ripple at the chopping frequency by approximately 60 dB. The LPF attenuates the ripple at twice the chopping frequency by a factor of 5 and reduces the peak-topeak output fluctuations by 2.5×. Fabricated in a 40nm CMOS technology, the presented bandgap reference consumes 25 μA from a 2.5V supply and occupies an area of 240 μm x 180 μm.

Keywords: Analog Circuits and Systems, Bio-signal Amplifiers, Sensor Interface Circuits and Microsystems
Abstract: This paper presents a novel Capacitively Coupled Chopper Instrumentation Amplifier (CCIA) architecture that substantially mitigates the key design trade-offs between power, bandwidth, offset-induced ripple, and noise in precision analog front-ends. By employing a tightly controlled, single-stage regenerative feedback core, the amplifier achieves a high open-loop gain (>140dB) and an 8.7 MHz Gain-Bandwidth (GBW) product while consuming a total supply current of 12μA. The central paradigm shift of this architecture is the implementation of an infrequent auto-zeroing scheme that is deliberately decoupled from the much faster continuous chopping frequency (25 kHz). This intermittent operation periodically resets floating input nodes, enabling entirely resistorless biasing that mitigates leakage-induced drift. By maintaining the auto-zeroing frequency orders of magnitude below the chopping frequency, this mechanism substantially reduces the kT/C noise folding penalty, charge injection and dynamic power consumption. By periodically nulling the offset, the design significantly suppresses the output ripple to 80 μV, demonstrating a highly effective approach for high-precision, low-power sensor interfaces.

Keywords: Analog Circuits and Systems, Sensor Interface Circuits and Microsystems, Integrated Biomedical Systems
Abstract: This paper presents a high-precision, energy-efficient capacitively-coupled chopper gain amplifier (CCGA) employing a loop regulation ripple reduction (L3R) technique. The proposed L3R scheme enhances attenuation of offset-induced ripples and output drift while consuming minimal current. By strategically implementing L3R scheme, the technique effectively suppresses the dominant first-stage offset without compromising noise performance. Implemented in a 180 nm CMOS process, the amplifier operates from a 1.8 V supply while consuming 1.8uA current. Simulation results demonstrate an input-referred noise density of 111.4nV/√Hz and a competitive gain-bandwidth (GB) efficiency of 514MHz/mA and a noise efficiency factor (NEF) of 5.4, establishing the proposed architecture as a compelling solution for high-precision, low-power sensor interface applications.

Keywords: Machine Learning at the Edge, Other AI and Edge Topics, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Despite significant advancements in machine learning, AMD’s GPU power saving algorithms have yet to benefit from the potential of these techniques. Traditional power management strategies in AMD GPUs predominantly rely on static and heuristic based methods, which often fail to adapt dynamically to varying workloads and operating conditions. Machine learning algorithms, with their ability to learn from large datasets and predict complex patterns, offer a promising alternative. They can enable more granular and adaptive power management by anticipating workload demands and optimizing system settings in real-time. There are major constraints on exploring these solutions on silicon as there are limitations on software support, hardware restrictions and timing closure on products that have not been designed with machine learning use cases in mind. GPS overcomes these constraints by creating a software model to assess machine learning models without the need to implement the full solution on silicon.

Keywords: Neuromorphic Circuits and Systems, Human/brain-Machine Interfaces, Digital Integrated Circuits
Abstract: This paper presents a fully synthesizable, tree-based Address-Event Representation (AER) encoder designed for scalable neuromorphic computing systems. To achieve high throughput while maintaining strict compatibility with commercial EDA workflows, the asynchronous design employs a bundled-data protocol within a semi-decoupled micropipeline. The architecture replaces traditional transparent latches with standard edge-triggered flip-flops, enabling digital synthesis and place-and-route (PnR) using Cadence toolkits. A cross-coupled NAND-based random-priority arbiter is embedded within the encoder of each tree node to resolve event collisions efficiently. An 8-event AER prototype is fabricated in 65 nm CMOS technology utilizing a purely digital standard-cell flow. Post-fabrication silicon measurements validate the design, demonstrating a peak throughput of 33 MEvent/s and an average event latency of 50 ns, equating to a propagation delay of 17 ns/(event-bit). The design consumes only 435 fJ per encoded event.

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems
Abstract: This paper presents a design automation and optimization framework for current-source DACs. A thermometercoded DAC is implemented in TSMC 65-nm technology with a 1.2 V supply and optimized for key performance metrics, including resolution, INL, DNL, and ENOB. The proposed approach initializes circuit parameters in a design-aware manner based on user-defined specifications and iteratively optimizes them for power under nominal conditions, followed by ProcessVoltage-Temperature (PVT) corner and Monte Carlo simulations to ensure robustness against variations and mismatch. The framework demonstrates scalability across resolutions from 5 to 12 bits, achieving sampling rates from 180 MS/s to 2.7 MS/s while maintaining high linearity under optimized power.

Keywords: In-Memory Computing Circuits and Systems, AI Digital Hardware, Accelerators, and Circuits, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: Analog compute-in-memory (CIM) has recently emerged as a novel paradigm for artificial intelligence compute, but the efficiency of CIM is heavily bottlenecked by the energy and area overhead of analog-to-digital (ADC). While replacing high-precision ADCs with 1-bit conversion significantly reduces peripheral overhead, binarization of crossbar-level partial sums introduces substantial information loss, leading to accuracy degradation. Therefore, aggressive partial sum binarization for high-precision (multi-bit) workloads remains a significant challenge for CIM.In this work, we address this challenge by proposing a synergistic framework combining ADC-free quantization with novel mapping schemes. We first established the insight that computations on the most/least significant bits (MSB/LSB) exhibit different sensitivities to ADC quantization errors. Exploiting this insight, we propose a novel mapping scheme to maximize system efficiency while maintaining near-lossless functional accuracy. First, we propose to use 1 bit/cell for MSB and 2-3 bits/cell for LSB, which is termed ``unbalanced bit-slicing" (UBS). Second, we map the MSBs and LSBs to subarrays with different sizes (``array-split"). Simulation results on ResNet20/CIFAR-10 demonstrate up to 12times energy and 18.6times area efficiency improvement over the conventional CIM baseline with 6-bit ADCs. We further verified the error resilience of the proposed weight-mapping scheme based on the characteristics of fabricated ReRAM test chips. Our ADC-free framework demonstrates elimination of the ADC bottleneck and variability-resilient near-lossless inference accuracy on standard benchmarks.

Keywords: Quantum Architecture and Design, Other Beyond CMOS Topics, Other AI and Edge Topics
Abstract: This article presents a deep-learning-assisted modeling framework for automated Cryo-CMOS parameter extraction from 298 K down to 4.2 K. Our approach utilizes a physics-guided decoupled neural network architecture to eliminate gradient conflicts, which enables simultaneous calibration of typical characteristics and statistical process variations while achieving continuous-temperature simulation through lightweight neural approximations. Accordingly, the extracted models capture key device-level parameters across full temperature range with fitting errors below 6%, and demonstrate close correlation with fabricated 101-stage ring oscillator characteristics across multiple process corners, validating the proposed modeling strategy for scalable quantum computing applications.

Keywords: Signal Processing Theory and Methods, Digital Integrated Circuits
Abstract: Accurate thermal modeling is essential for reliable operation of modern integrated circuits (ICs), where power densities continue to increase with technology scaling. This paper presents a two-stage frequency-domain approach for extracting the thermal impulse response (kernel) of an IC from multiple power–temperature map pairs. In the first stage, Wiener deconvolution recovers a raw two-dimensional kernel from training data. In the second stage, the radial profile of the extracted kernel is fitted to a tri-exponential model using sequential quadratic programming, yielding physically interpretable parameters corresponding to distinct thermal spreading mechanisms in the chip stack. The extracted kernel enables rapid temperature prediction for arbitrary power distributions via a single FFT based convolution. Simulation validation on a synthetic quad-core processor model demonstrates a 2D kernel correlation of 0.99 with the ground truth and temperature reconstruction with root-mean- square error of 0.108◦C and correlation exceeding 0.9995 across unseen test configurations.

Keywords: Emerging Memory and Memristor, Other Beyond CMOS Topics, MEMS/NEMS and Nano-Electronics
Abstract: Hafnia-based ferroelectric and antiferroelectric materials exhibit strong history-dependent hysteresis and rate-sensitive domain dynamics. The latent oscillations and stochastic switching behaviors make these materials promising candidates for designing artificial synapses and neurons for neuromorphic computing. However, existing compact models fail to capture essential behaviors or impose prohibitive computational costs. In this work, we propose a physics-informed LSTM compact model that embeds domain-level dynamics into the recurrent gates and verify our design in Cadence. Calibration on two hafnia-based ferroelectric and antiferroelectric capacitors achieves a mean R² of 0.99 when fitting the charge-voltage curves and shows promising behavior on unseen stimuli.

Keywords: Analog Circuits and Systems, Mixed-Signal RF and Baseline Circuits, Other Analog/RF Circuits and Systems
Abstract: Extracting threshold voltage (Vth) is of prime im portance in low-power design of CMOS circuits. The tradi tional square-law method of threshold voltage extraction fails to perform in deep sub-micron technology due to the issue of mobility degradation. In this work, a robust continuous-time threshold voltage extractor using the gm/ID sizing technique is proposed that naturally accounts for all the short channel effects. The proposed architecture is designed using SCL CMOS 0.18 µm process technology. The design has been validated using schematic simulations across the industrial temperature range of-40°C to 125°C. The extraction error is-0.71% to +0.65% for the above temperature range at typical-typical (TT) corner. The proposed design also shows remarkable PVT robustness, with deviations kept within ±1.5% across all extreme design corners and even at supply voltage scaling from 1.8 V to 1.0 V. The design also works at a minimum supply voltage of 1.0 V with a PSRR of 51 dB at 100 kHz.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Mixed-Signal RF and Baseline Circuits, 5G & 6G Circuits and Systems
Abstract: This work presents a spur-reduction technique for high multiplication-factor PLLs employing a switched-capacitor loop filter, achieving a compact core area of 0.136mm^2. In such architectures, reference spurs arise from periodic disturbances at the VCO control node caused by transconductor mismatch, chopping-switch non-idealities, and switching-induced charge injection. To mitigate this effect, a foreground feed-forward calibration scheme is proposed that senses and cancels the steady-state error at the transconductor input. The calibration is performed once at startup after the PLL achieves lock and can be disabled thereafter. This procedure compensates the transconductor input offset and restores the optimal operating range of 350-600mV. As a result, reference spurs are suppressed to approximately -75dBc across PVT variations while limiting the transconductor jitter contribution to below 150fs. The concept is validated in a 24-29GHz SSPLL using parasitic-extracted simulations and can be extended to conventional charge-pump PLL architectures with minor modifications.

Keywords: RF Front-End Circuits, Physical Design, Test, Verifications, Other Analog/RF Circuits and Systems
Abstract: This paper presents a sub-THz communication link using a 16-nm FinFET direct-digital modulation transmitter and a 0.6 m circular hollow plastic (PTFE) waveguide. The transmitter performs high-order modulation directly at carrier frequencies and implements on-chip amplitude and phase calibration to mitigate I/Q mismatch. The transmitted signal is coupled from a rectangular metal waveguide into a circular hollow plastic waveguide through a probe antenna and a 3D stereolithography (SLA) printed resin coupler, enabling efficient mode conversion and low-loss propagation. The 0.6m prototype data link operates at D-band (140 GHz) and achieves 32 Gb/s 16-QAM data transmission with a measured EVM of -21.1 dB without extensive offline equalization. The transmitter has 235 mW DC power. The proposed system demonstrates the feasibility of using hollow plastic dielectric waveguides as a low-cost, high spectral efficiency, and energy-efficient interconnect solution for short-range sub-THz communication links.

Keywords: RF Front-End Circuits, Linear and Non-linear Analog Systems, Other Analog/RF Circuits and Systems
Abstract: This paper presents an analytical model of the Dickson charge pump passive envelope detector (ED) that captures the impact of temperature variation and process-dependent device parameters on conversion gain and charge-up time. A comparison between planar bulk CMOS and FinFET technologies is presented, highlighting the advantages of FinFET devices for passive ED implementations. To validate the model, a receiver prototype is fabricated in GF 12 nm FinFET process and is characterized across a temperature range of 0 to 50 °C. Measurement results show strong agreement with the model, validating its accuracy in capturing temperature-dependent behavior. The proposed model provides insight for the design of temperature-robust low-power receivers.

Keywords: Analog Circuits and Systems, RF Front-End Circuits, Mixed-Signal RF and Baseline Circuits
Abstract: This paper investigates low-parasitic ESD protection schemes for a 28-GHz mmWave RF front-end implemented in 22-nm CMOS technology. Diode-based and DSCR-based ESD devices are evaluated using series/parallel inductor and LC tank isolation topologies. The series LC tank achieves the best tradeoff, providing excellent RF performance, wide-band operation up to 50 GHz, and minimal inductor area.

Keywords: Human/brain-Machine Interfaces, Implantable/injectable Systems, Bio-signal Amplifiers
Abstract: Advances in miniaturised implantable neural electronics have paved the way for therapeutic brain–computer interfaces with clinical potential for movement disorders, epilepsy, and broader neurological applications. This paper presents a mixed-signal analogue front end (AFE) designed to record simultaneously both extracellular action potentials (EAPs) and local field potentials (LFPs). The feedforward path integrates a low-noise amplifier (LNA) and a successive-approximation-register (SAR) analogue-to-digital converter (ADC), while the feedback path employs a fixed-point infinite-impulse-response (IIR) Chebyshev Type II low-pass filter to suppress sub-mHz components via bulk-voltage control of the LNA input differential pair using two R–2R pseudo-resistor digital-to-analogue converters (DACs). The proposed AFE employs a low-power (LP) mode and an offset-cancellation high-performance (HP) mode. The proposed AFE achieves 40.55 dB gain and supports neural recording from 0.1 Hz to 5.705 / 9.66 kHz (LP / HP), with typical input-referred noise of 3.9 / 6.615 uVrms in the LFP band and 11.42 / 11.11 uVrms in the EAP band (LP / HP). Its typical power per channel is 5.44 uW (LP) and 11.35 uW (HP), while it occupies 0.198 mm2.

Keywords: Implantable/injectable Systems, Analog Circuits and Systems, Mixed-Signal RF and Baseline Circuits
Abstract: Closed-loop neuromodulation based on bladder pressure feedback is a promising approach for lower urinary tract dysfunction, but it requires reliable wireless recovery of physiological feedback under strict implant constraints. This paper presents a 4 MHz miniaturized inductive on-off keying (OOK) receive chain for bladder pressure feedback. The proposed system recovers pressure data transmitted from an implantable urodynamics monitor and sends the recovered bitstream to the Networked Neural Prosthesis (NNP) module for threshold-based stimulation control and real-time monitoring. The receiver consumed 2.63 mA from a 3.3 V supply and achieved an input sensitivity of -74 dBm at the AFE input using a packet error rate of 20% as the criterion. Benchtop experiments verified wireless packet recovery and demonstrated the tradeoff between antenna size, transmission range, and implantability. An in vivo pig experiment further validated the functional pathway from implantable bladder pressure sensing and wireless data recovery to downstream stimulation output. These results support the proposed receive chain as a practical foundation for future fully implanted closed-loop neuromodulation systems.

Keywords: Neuromorphic Circuits and Systems, Analog, Digital and Mixed Signal Processing, Human/brain-Machine Interfaces
Abstract: This paper presents the design and implementation of an asynchronous delta modulator as a spike encoder for event-driven neural recording in a 65nm CMOS process. The proposed neuromorphic front-end converts analog signals into discrete, asynchronous ON and OFF spikes, effectively compressing continuous biopotentials into spike trains compatible with spiking neural networks (SNNs). Its asynchronous operation enables seamless integration with neuromorphic architectures for real-time decoding in closed-loop brain–machine interfaces (BMIs). Measurement results from silicon demonstrate an energy consumption of 60.73 nJ/spike, an F1-score of 80% compared to a behavioral model of the asynchronous delta modulator, and a compact pixel area of 73.45 μm × 73.64 μm.

Keywords: Human/brain-Machine Interfaces, Bio-signal Amplifiers, Biomedical Signal/Image Processing
Abstract: In this work, a fully integrated modular, high-performance neural interface system comprising a 32Ch Analog Front End (AFE) recorder and a multichannel biphasic current stimulator (PulseStim) is developed, for concurrent real-time electrocorticogram (ECoG) co-acquisition with commercial neural platforms. A custom-built passive parallel adapter enables co-recording by splitting the signal from the ECoG electrodes array to both the developed system (DS) and the commercial setup (CS) [Intan RHD2132 Headstage + Open Ephys]. Validation was conducted with anesthetized mice, where a 32Ch NeuroNexus ECoG electrodes array was positioned over the bilateral sensorimotor cortex, and the left sciatic nerve was electrically stimulated (500µA–1000µA; 100µs–200µs) via hook electrode using PulseStim to evoke reproducible cortical Somatosensory Evoked Potentials (SEPs). The developed system provides waveform level agreement with the commercial reference, yielding a correlation value (r) of 0.94 across 5 averaged stimulation trials, with a system noise floor of 1.69µVrms. The developed AFE demonstrates a passband max gain of 46dB, having −3dB bandwidth of 0.5Hz−524Hz, and THD levels below 0.06% for input amplitudes >3µV, establishing a low noise, scalable solution for neural recordings.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Other Areas in Biomedical Circuits and Systems
Abstract: This paper presents a 4th-order low-pass filter (LPF) for biopotential signal acquisition targeting a 100-Hz cutoff frequency. A combined current-cancellation (CC) and gain-compensation (GC) subthreshold source-follower (SSF) biquad is proposed, where a cross-coupled PMOS compensation path restores the DC gain to approximately 0 dB by compensating for body-effect-induced gain loss. Expressions for the unity-gain condition, cutoff frequency, quality factor, and input-referred noise (IRN) are derived. The 4th-order filter cascades a PMOS SSF biquad (Stage 1) and an NMOS CC+GC SSF biquad (Stage 2) operating at a 1.0 V supply. Spectre simulations show a -3 dB frequency of 100.9 Hz and a DC gain of 15.53 mdB (approximately 0 dB), total power consumption of 6.67 nW, an integrated input-referred noise (IRN) of 33 µVrms over 0.1-100 Hz, and an HD3 of -57.29 dB at 60 Hz with a 10-mV peak-to-peak sinusoidal input.

Keywords: Neuromorphic Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neural Networks and Fuzzy Logic
Abstract: Predictive SAR-ADCs require suitable predictors showing high accuracy with minimum hardware effort. In this paper neural network based predictors are evaluated and compared with kalman filters and linear prediction filters. Prediction gain is used as the performance metric to analyze neural network architectures with different input layers. A novel lower bound of the required prediction gain for predictive SAR-ADC operation is introduced. A proposed neural predictor achieves an approximately constant wideband prediction gain of 30 dB over the entire frequency band. Kalman filter and linear predictor only provide a reasonable gain up to 0.3 nyquist-frequency and with mostly lower prediction gains. Furthermore, the neural predictor requires only 19.8% of the multiply–accumulate (MAC) operations of the Kalman filter, while providing superior performance in broadband applications.

Keywords: Neural Learning Circuits & Systems, Neuromorphic Circuits and Systems
Abstract: Reservoir Computing (RC) provides an efficient framework for temporal signal processing by leveraging fixed nonlinear dynamical systems while training only a linear readout layer. In this work, we present a fully transistor-level analog reservoir architecture composed of 24 parallel nonlinear dynamic nodes implemented in 40 nm CMOS process. Each node generates distinct temporal dynamics through controlled variations in bias voltages, transistor dimensions, and capacitance values, enabling heterogeneous state responses under a common input excitation. The architecture is validated through three benchmark tasks: Henon-maps chaotic time-series forecasting, second-order nonlinear dynamic system prediction, and EEG epileptic seizure classification. The proposed reservoir architecture successfully predicted Henon-map series trajectory with 0.015 NMRSE. Also, it achieved 0.000194 NMSE for nonlinear system recognition and 100% classification accuracy on a balanced EEG seizure dataset. The results demonstrate that compact CMOS nonlinear dynamics can serve as powerful hardware reservoirs for both forecasting and biomedical signal classification applications.

Keywords: 5G & 6G Circuits and Systems, Communications Circuits, Theory and Applications, Other Analog/RF Circuits and Systems
Abstract: This paper presents a neural network assisted self-interference cancellation (SIC) technique for millimeter-wave (mm-wave) in-band full-duplex (IBFD) transceivers in the RF and analog baseband domains in the presence of practical nonidealities. First, the proposed technique predicts the RF and analog baseband canceller parameters utilizing two neural networks using the signals from the transmitter and the receiver. Next, the final values of the canceller parameters are obtained using an optimization algorithm within a narrow range (±10% of the full range) around the predicted values of the parameters. By restricting the search space, the time required to determine the canceller parameters can be reduced significantly.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Other Analog/RF Circuits and Systems
Abstract: This paper presents a machine learning (ML) framework that integrates LightGBM quantile regression with Bayesian optimization to autonomously discover optimal pre-emphasis parameters that maximize Eye-SNR at the receiver. Because optimal configurations represent fewer than 1% of the parameter space, a stacked quantile regression ensemble modeling the 50th, 90th, and 99th percentiles is employed to capture rare peak signal-integrity behaviors, achieving R2 = 0.96. Optuna’s Tree-structured Parzen Estimator then efficiently searches the discrete parameter space, converging within 100–150 trials. The framework is validated on two held-out cables across three data rates, achieving 82–97% of the best-observed Eye-SNR from a systematic sweep as confirmed by independent transistor-level circuit simulations.

Keywords: Physical Design, Test, Verifications, Analog Circuits and Systems
Abstract: A printed circuit board (PCB)-based charge detection mass spectrometry (CDMS) detector is presented for measuring particles in the size range from 1 to 10 um in diameter and charges between 5 and 100 ke-. The detector replaces handcrafted electrodes with patterned PCB electrodes, improving manufacturability, geometric precision, and mechanical robustness. A custom charge amplifier is used to amplify the image charge induced on the PCB electrodes. The detector is tested with 5 μm polymethyl methacrylate particles and demonstrates improved detector range and accuracy over previous designs.

Keywords: Sensor Interface Circuits and Microsystems, Analog, Digital and Mixed Signal Processing
Abstract: This work presents a discrete printed circuit board (PCB) implementation of an analog front-end (AFE) for the second harmonic (2-ω) technique proposed to accurately measure the AC magnetic field using a Hall-effect sensor. Traditionally, the use of current spinning (CS) techniques required by the Hall-effect sensors to reduce the offset and induced noise limits the overall systems bandwidth. 2-ꞷ technique addresses this limitation by generating a low offset and no induced voltage output. This technique requires the Hall-effect sensor to be biased with a sinusoidal excitation current along with an alternating magnetic field of the same frequency, resulting in the generation of a frequency component to be measured at the second harmonic of the Hall-effect sensor output. While the 2-ꞷ technique has been reported previously, this work focuses on the development of a compact PCB-based AFE to experimentally implement the 2-ꞷ approach and isolate the generated 2-ꞷ component from the Hall-effect sensor output while suppressing the undesired frequency components at ꞷ. Experimental measurements of the designed AFE demonstrate functional validation for a range of frequencies from 500 Hz to 2 kHz, achieving an overall measured system sensitivity of approximately 8.3-14.4 mV/mT. The proposed design demonstrates the feasibility of implementing compact magnetic sensing and measurement systems using discrete analog circuitry.

Keywords: Sensor Interface Circuits and Microsystems, Analog Circuits and Systems, MEMS/NEMS and Nano-Electronics
Abstract: We present a fabricated local back-gated (LBG) graphene Hall sensor (GHS) integrated with an analog conditioning circuit. The sensor independently achieves record-low flicker noise through significant trap density reduction near or on the graphene channel. This is realized via prolonged vacuum annealing, seed-layer engineering, and robust passivation. The conditioning circuitry further suppresses the residual noise, while a spinning current technique (SCT)-based analog frontend (AFE) dynamically eliminates offset voltages and low-frequency noise components.

This combined device–circuit approach enables 1 Hz magnetic field detection at the thermal noise floor. The optimized LBG-GHS demonstrates flicker-noise corner frequencies of 32.5 Hz at the driving terminal and 0.6 Hz at the sensing terminal, surpassing prior reports of sensing-terminal corner frequencies (>100 Hz) by up to 100×. Furthermore, we report for the first time GHS operation at the thermal noise floor of 29 nV/√Hz, corresponding to a magnetic field resolution of 342 nT/√Hz when interfaced with the SCT-based AFE.

Keywords: Analog, Digital and Mixed Signal Processing, Image and Video Compression, Image, Video and Multi-Dimensional Signal Processing
Abstract: Imaging using event-based sensors (EBS) encodes brightness changes as asynchronous events with high temporal resolution and wide dynamic range. However, in the conventional EBS, log-domain signal amplification and thresholding are ill-conditioned near zero photo-intensity: small noise fluctuations map to large post-logarithm swings that trigger false events. We address this issue by introducing an adaptive technique to tune the photoreceptor based on the scene brightness. The circuit reduces the photoreceptor bandwidth under dim conditions to reject noise and increases it under bright conditions to retain motion fidelity. Simulations show that the proposed technique reduces the peak false-positive (FP) rates by over 90% relative to a fixed-bandwidth design during dark conditions while simultaneously reducing the false-negative (FN) rate by 81% in bright conditions compared to the unfiltered baseline.

Keywords: Regulators, References and Reliability Methods, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a curvature-compensated voltage reference which incorporates first- and higher-order temperature correction to compensate both the T and T ln T dependence of the gate-source voltage (VGS) of a transistor operating in the subthreshold region. It also boasts of a current-steering digital to-analog converter (DAC) that enables fine output voltage level trimming with 1 mV resolution and up to ≥125 mV adjustment range, without degrading temperature coefficient (TC). 200 Monte Carlo (MC) simulations across process and mismatch variation shows the circuit achieves a mean TC of 4.29 ppm/◦C and a spread of 0.42 ppm/◦C from −40◦C to 125◦C. The power supply ripple rejection is −85.02dB and the coefficient of

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a low-side MOSFET current sensor that utilizes a cross-coupled input stage for amplifier, which provides 2x improvement in transconductance, gain and bandwidth, compared to a current sensor with a conventional amplifier, resulting in enhanced current sensing accuracy. Current sensors using both the proposed and the conventional amplifiers are designed and simulated in 130 nm BCD technology. Simulations across the process, voltage, and temperature (PVT) corners show a minimum gain of 46.94 dB, a bandwidth of 45.23 MHz, and a phase margin of 68.02◦. The current sensor with the proposed amplifier, compared to the conventional amplifier, provides gain and bandwidth improvements of more than 7 dB and 5x, respectively, over the PVT corners, with almost the same power consumption. The proposed current sensor also shows more than 13x reduction in sensing current error for load currents up to 1.5 A.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Other Power Circuits and Systems
Abstract: This paper presents the design and implementation of a coupled controller and state observer for voltage control of a DC-DC Buck converter. The design methodology is based on the pole placement technique in the state-space domain, where the system is augmented with an integral state to ensure zero steady-state error. The state observer was designed with significantly faster poles to guarantee a rapid convergence of the estimation error. The main contribution of this work is the textbf{complete hardware realization} of both the control system and observer in a textit{Field-Programmable Analog Array} (FPAA). This implementation demonstrates the feasibility of using reconfigurable analog architectures for high-performance control signal processing, validating the robustness of the pole-placement approach in an analog hardware environment.

Keywords: Other Power Circuits and Systems, Converters, ADC, DAC and others, Linear and Non-linear Analog Systems
Abstract: Switched-capacitor DC–DC converters are widely used for fully integrated on-chip power supplies due to their high efficiency and compact footprint. Existing design approaches provide effective circuit analysis but limited guidance for systematic circuit-level design. This work presents a topology-independent design methodology based on a static ohmic-loss model and the boundary between full and partial transfer. By using the boundary as the design target, capacitance allocation, MOSFET sizing, and clock period are jointly optimized while ensuring simultaneous boundary operation of all flying capacitors. The resulting design flow is demonstrated on a telescoping-stage converter. Simulation results closely match theoretical predictions and confirm minimum-loss operation, providing a practical and systematic framework for SC converter design.

Keywords: Hardware Security, Hardware-Software Co-Design, Other Digital Circuits and Systems
Abstract: The prolific deployment of embedded systems across critical infrastructure has made hardware security a pressing concern. For example, inexpensive microcontrollers, such as the STM32 series, are frequently deployed with cryptographic firmware that is vulnerable to Side-Channel Attacks (SCA), including Correlation Power Analysis (CPA). Subsequently, manually implementing existing software-based countermeasures, including random delays and instruction shuffling, can be difficult, tedious, and error-prone. This work presents an automated, toolchain-agnostic framework that secures existing firmware by injecting random jitter and dummy instructions at the assembly level. Furthermore, a software-based AES-128 implementation on an STM32F446RE is used to validate the proposed framework using a minimalist power-analysis setup. Evaluation indicated that the average Guessing Entropy (GE) increased from 75.9 at baseline to 153.5, rendering key recovery impractical. Moreover, the proposed framework suppressed maximum correlation to noise levels (p_max = 0.039) across all 16 key bytes, resulting in a 0% CPA success rate. In addition, the hardening techniques are lightweight and remain suitable for resource-constrained environments.

Keywords: Hardware Security, Hardware-Software Co-Design, Other Digital Circuits and Systems
Abstract: Physical Unclonable Functions (PUFs) are widely used for lightweight device authentication; however, conventional Arbiter PUFs remain vulnerable to Machine Learning (ML) modeling attacks due to their static and memory-less challenge–response pair (CRP) behavior. This work proposes a history conditioned N-XOR-APUF that introduces a deterministic temporal state into the challenge transformation process by generating a history-aware challenge from previous responses instead of directly evaluating the external challenge. This lightweight modification disrupts the linear additive structure exploited by ML attacks while preserving low hardware overhead. Experimental results show significant degradation in prediction across multiple attack models: Logistic Regression (LR), Support Vector Machine (SVM), Multi-Layer Perceptron (MLP), and black-box (CMAES) achieve 52.84%, 50.84%, 52.03%, and 49.88% accuracy, respectively. These results demonstrate improved resistance to linear, nonlinear, and evolutionary modeling attacks without requiring complex obfuscation mechanisms or external secret keys.

Keywords: Hardware Security, Hardware-Software Co-Design, Other Digital Circuits and Systems
Abstract: The robustness of unsupervised hardware trojan (HT) detection using Physical Unclonable Function (PUF) derived data remains not fully understood, especially when trojans induce subtle, noise-like perturbations. This work performs a controlled, drift-aware evaluation by injecting multi-σ statistical deviations into golden CRPs across three Arbiter PUF architectures, including FPGA implementations on the Xilinx PYNQ-Z2 (Zynq-7020) platform with on-chip delay-based PUF cores and CRP extraction via UART. To ensure generality beyond a single design, results are validated against publicly available FF-APUF datasets, enabling cross-architecture comparison under identical perturbation conditions. Quantitative analysis shows detectability drops sharply with realistic low-energy drift accuracy remains high at ∼96–99% for σ ≤ 0.02, degrades to ∼87–94% at σ = 0.07, drops to ∼78% at σ = 0.20, and approaches near-random (∼54%) at higher σ. These results indicate that subtle trojans become indistinguishable from intrinsic PUF noise well before observable performance degradation. Unlike prior work assuming clear separability, this study maps detectability breakdown under controlled drift, establishing clear quantitative limits of unsupervised PUF-based trojan detection.

Keywords: Hardware Security, Linear and Non-linear Analog Systems, Physical Design, Test, Verifications
Abstract: We present the first experimental hardware demonstration of a physically unclonable function (PUF) based on higher-order harmonic distortion of standard CMOS inverters. Unlike traditional PUFs that rely on SRAM initialization randomness or oscillator delay, this approach treats distortion — quantified via the Integral Function Method (IFM) — as a physics-governed security primitive measurable directly from a device's voltage transfer curve. Measurements on two commercially available inverter families, CD4069 (5V thick-oxide CMOS) and SN74HC04 (high-speed HCMOS), confirm that 2nd-order (HD2), 3rd-order (HD3), and total harmonic distortion (THD) fingerprints are consistent, distinguishable across device familie,s and sensitive to manufacturing variations in real silicon chips. By using DAC-controlled quasi-static DC and AC sweeps, the system creates a large set of challenge–response pairs. Analysis of inter-device and intra-device Hamming distances, even in the presence of DAC threshold noise, confirms that the PUF achieves strong uniqueness and repeatability—two key requirements for secure hardware identification. Overall, the study demonstrates that IFM-based harmonic distortion is a practical and experimentally validated foundation for hardware security applications, including establishing a root of trust and monitoring integrated circuit aging.

Keywords: Wireless Mobile Circuits and Systems and Connectivity, Technologies for Smart Sensors, RF Front-End Circuits
Abstract: This paper presents a guard-based technique to reduce the effect of RF front-end capacitance on antennaintegrated SAR proximity sensing in compact wireless devices. When the antenna itself is reused as the sensing electrode, the measured capacitance depends not only on body proximity but also on the connected RF front end, whose capacitance can vary with operating state. This forces conservative sensing thresholds, causing premature transmit-power backoff and unnecessary throughput loss. The proposed method splits the RF blocking capacitor and drives the intermediate node with the guard waveform through an RF choke, thereby substantially isolating the RF front-end capacitance from the main sensing path. The method improves sensing accuracy while preserving the compact antenna-integrated architecture.

Keywords: Other Sensory Circuits and Systems, Hardware-Software Co-Design, Signal Processing Theory and Methods
Abstract: This paper presents a hardware-efficient MIMO radar architecture that enables coarse spatial classification without digital beamforming or angle-domain processing. Instead of relying on phase-coherent virtual array formation, spatial discrimination is achieved through static directional transmit and receive antenna patterns that segment the observable space into predefined regions. A custom 60 GHz FMCW radar system with directional antenna arrays was developed and fully integrated on a single PCB. Spatial zones are determined through transmit–receive channel combinations and amplitude-based evaluation of the received signals. The complete radar signal acquisition and processing pipeline, including range FFT and spatial classification, is executed on a low-power STM32 microcontroller without external DSP or FPGA resources. Experimental validation demonstrates reliable range detection and spatial discrimination using the proposed architecture. Compared to conventional MIMO radar systems requiring beamforming and phase-based angle estimation, the presented approach significantly reduces computational complexity and system requirements while maintaining effective spatial target separation. The architecture therefore enables compact, low-power radar sensors suitable for embedded and resource-constrained sensing applications.

Keywords: Other Sensory Circuits and Systems, Sensor Interface Circuits and Microsystems, Analog, Digital and Mixed Signal Processing
Abstract: This work presents a simulation framework for analyzing a multi-pixel LiDAR system that combines fiber-based and free-space optical paths, building on prior experimental demonstrations of the architecture. The simulator models signal acquisition using real-world datasets (Middlebury 2006) while incorporating light attenuation, lens shading, beam spreading, and random amplitude and phase fluctuations. Raster scanning is used to emulate photon arrivals, detector deadtime, and interference effects, enabling evaluation of range accuracy and signal-to-background performance. Simulation results indicate that the dual-path architecture can improve ranging precision by over 25% and maintain normalized accuracy above 0.9 under moderate attenuation within the assumptions of the proposed model. These results illustrate the utility of the simulation framework for exploring architecture-level trade-offs in future multi-pixel FMCW LiDAR systems.

Keywords: Hardware Security, RF Front-End Circuits, Sensor Interface Circuits and Microsystems
Abstract: This paper presents a measurement-driven approach for interconnect reliability monitoring using integrated on-chip antennas and circuit-level readout simulations. An interconnect–antenna stack is fabricated and evaluated under controlled void conditions, showing reduced differential-mode coupling with increasing resistance. Readout simulations convert antenna signals into frequency-domain power spectra for system-level monitoring.

Keywords: Signal Processing Theory and Methods, Image, Video and Multi-Dimensional Signal Processing, Other Signal and Image Processing
Abstract: This work proposes an adaptive multiple-time-step forecasting framework for time series analysis utilizing empirical signal decomposition and ensemble modeling. To address varying temporal dynamics, this work proposes an algorithm that adjusts the forecasting horizon for each decomposed component based on its spectral content. The proposed approach, termed Adaptive Multiple-Time-Step Signal Forecast, aims to improve long-term accuracy by optimizing component-specific predictions. This method is compared with standard approaches using two regression techniques: LSTM, and XGBoost. Experimental results on three synthetic time series and hourly Romanian electricity consumption/production data indicate that the adaptive approach, especially when implemented with XGBoost, delivers high forecasting performance.

Keywords: Other Signal and Image Processing, Signal Processing Theory and Methods, Other Digital Circuits and Systems
Abstract: Information in the Appendix explains that PA researchers will be first in U.S. to create firefly inventories in the biological science area. Other PA adaptive signal processing researchers used the Lévy Firefly Algorithm (LFFA) that combines the Firefly Algorithm based on how fireflies interact through flashes and a random-step function using the Lévy distribution. Theoretical background materials have been previously published to explain how the LFFA can be effectively used in IIR adaptive filters designed with second order coupled-form sections and adaptive lattice-ladder structures which are low sensitivity structures that have existed in the literature for many decades.

Keywords: Biomedical Signal/Image Processing, Other AI and Edge Topics, Other Areas in Biomedical Circuits and Systems
Abstract: Federated learning (FL) enables collaborative model training across institutions without sharing sensitive patient data. However, the inherent heterogeneity of electrocardiogram (ECG) data across healthcare providers presents significant technical challenges for robust classification. We propose FedDualAtt, a personalized federated learning approach that splits transformer attention heads into global and local branches. Global heads are aggregated via FedAvg to capture shared cross-site patterns, while local heads remain client-specific to adapt to institution-level recording characteristics. Experiments on FedCVD, an FL benchmark for cardiovascular disease detection, demonstrate that FedDualAtt outperforms existing FL and personalized FL methods in ECG classification tasks. Analysis of global-local head ratios reveals that different clients benefit from varying levels of architectural personalization.

Keywords: AI-IoT Systems and Applications, Quantum Architecture and Design, Machine Learning at the Edge
Abstract: Federated learning (FL) enables collaborative model training across distributed devices without sharing raw data, making it suitable for privacy-sensitive robotic sensing applications. However, multi-agent systems generate heterogeneous and non-independent and identically distributed (non-IID) multimodal sensor streams that degrade conventional FL algorithms, while classical fusion modules introduce substantial parameter overhead and communication cost. This paper proposes QFedAgent, a hybrid quantum-classical personalized FL framework for multi-agent activity recognition. The approach integrates a variational quantum circuit (VQC) fusion module that models accelerometer--gyroscope interactions through quantum state encoding and entanglement, requiring only 72 quantum rotation parameters versus 33K in classical multi-layer perceptron (MLP)-based fusion, achieving approximately 10x total parameter reduction. Experiments on the OPPORTUNITY dataset under subject-based non-IID partitions demonstrate 97.7% mean test accuracy, confirming that parameter-efficient quantum fusion remains competitive with conventional federated baselines.

Keywords: Analog, Digital and Mixed Signal Processing, Signal Processing Theory and Methods, 5G & 6G Circuits and Systems
Abstract: Non-uniform sub-sampling (NUSS) and non-uniform discrete-time FIR (NUDTFIR) receivers enable blocker-tolerant RF front ends by spreading alias energy and introducing programmable rejection notches. However, conventional single-channel implementations are fundamentally limited by a single periodically time-varying response, which restricts the achievable notch depth and tuning flexibility. This work proposes a multichannel NUSS-NUDTFIR architecture that exploits harmonic transfer function (HTF) diversity across parallel full-rate branches. By generating each branch from a circularly shifted version of a base non-uniform sequence, the corresponding HTFs acquire deterministic phase rotations. Summing the branch outputs enables constructive combination of the desired down-conversion path while selectively canceling undesired alias-conversion components. The proposed framework enables adaptive notch placement, deeper rejection around selected alias bands near integer multiples of fs, and scalable operation from two to N channels. The approach provides a systematic and intuitive design methodology for interference-aware receiver front ends.

Keywords: Artificial Intelligence for Complex Networks and Nonlinear Systems, Other AI and Edge Topics
Abstract: As semiconductor technology scales, local layout-dependent effects (LLDEs) have become a significant factor in determining device performance, particularly in high-frequency RF applications. These effects often lead to significant discrepancies between schematic-level simulations and post-layout, leading to multiple design iterations. Additionally, the high-dimensional nature of LLDE variables makes exhaustive design space exploration via traditional SPICE simulations computationally burdensome. This paper introduces Metrics-Net, a multimodal surrogate model that uses deep learning to predict transistor performance from layouts. By processing image and numerical inputs together-combining LLDEs reflected layout images with numerical design parameters— Metrics-Net provides rapid and accurate predictions of critical transistor metrics f_{T}, f_{max}, from S-parameters and F_{min} from noise. Experimental results demonstrate that the proposed model achieves a 1,000-fold speed increase over conventional SPICE-based extraction and simulation with high accuracy. This acceleration enables an efficient search of the vast design space, allowing layout-aware transistor optimization in the early stages of the design.

Keywords: VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Converters, ADC, DAC and others, Physical Design, Test, Verifications
Abstract: This paper presents the design of a counter-based all-digital phase-locked loop (ADPLL) tailored for analog time-encoding design methodologies targeting systems and applications with long operational life cycles. The proposed PLL is implemented entirely in register-transfer level (RTL) to enhance portability across technology nodes. Portability is demonstrated by synthesizing the ADPLL in two distinct open-source processes—SkyWater 130 nm and IHP SG13G2—and analyzing the key differences observed during GDSII generation.Furthermore, the counter-based architecture is evaluated against its derivative time-to-digital converter (TDC)–based counterpart, highlighting improvements in both area efficiency and operating speed.

Keywords: Secure AI Hardware, AI-IoT Systems and Applications, Machine Learning at the Edge
Abstract: Recent advances in neural networks have improved medical diagnosis efficiency but raised privacy and security concerns for sensitive data such as ECG signals used in biometric identification. Homomorphic encryption enables secure processing of encrypted data but remains computationally intensive and vulnerable to fault-injection attacks. We propose an autoencoder-based framework for encrypted medical data, where the latent space is used for classification and the decoder reconstructs inputs. Reconstruction errors are used to estimate HE-induced noise and detect potential fault injections.

To improve efficiency, we employ parallel processing with rotation-saving techniques to mitigate CKKS rotation overhead, together with batch processing for acceleration. Experimental results show a 1.9× speedup over prior approaches, with improved security. Fault analysis is formulated as a numerical integrity-stress evaluation based on reconstruction residuals. The results indicate that the reconstruction branch provides a useful client-side integrity signal under numerical perturbations.

Keywords: Secure AI Hardware, AI-IoT Systems and Applications, AI Digital Hardware, Accelerators, and Circuits
Abstract: Fully Homomorphic Encryption (FHE) enables privacy-preserving inference for AI. In TFHE, comparisons are a major latency bottleneck because standard implementations evaluate them bit by bit. We accelerate encrypted comparisons using the mixed-radix Chinese Remainder Theorem (MRCRT). By restructuring an n-bit comparison into D = n/r sequential stages over r-bit digits and executing per-digit sub-comparisons in parallel, our MRCRT-based 64-bit comparator reduces latency by about 50% relative to the standard TFHE implementation. We integrate the comparator into privacy-preserving decision-tree inference and further exploit GPU parallelism. On a deep decision tree (25 layers, 115 nodes), the prototype achieves a 2× end-to-end speedup, and on a standard benchmark configuration, it provides about 22% lower latency than recent state-of-the-art private decision-tree methods.

Keywords: Communications Circuits, Theory and Applications, VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Digital Integrated Circuits
Abstract: Clock and data recovery (CDR) performance in high-speed communication systems is fundamentally determined by loop dynamics, stability margins, and jitter-tracking capability. This work presents a comprehensive loop-dynamics characterization of a digitally assisted baud-rate CDR architecture employing an analog time-encoding front end implemented using a voltage-controlled oscillator (VCO) and digital counter structure. A linearized small-signal model is developed to analyze key dynamic properties of the mixed-signal feedback system, including loop bandwidth, damping behavior, phase margin, and acquisition characteristics. The analytical framework is validated through behavioral simulation of the complete timing-recovery loop operating under representative communication channel conditions. System-level performance metrics including jitter tolerance (JTOL), bit-error rate (BER). The results demonstrate stable loop operation, predictable transient convergence, and reliable jitter tracking within the designed loop bandwidth. These findings confirm the robustness and implementation feasibility of the proposed time-encoded CDR architecture for high-speed mixed-signal communication systems.

Keywords: Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Designing a phase-locked loop (PLL) traditionally involves sequential optimization of individual circuit blocks followed by system-level integration. Such a hierarchical approach often leads to suboptimal global performance, as interdependencies among blocks are not jointly considered during parameter selection. In this work, a physics-informed neural inverse design framework that simultaneously optimizes all PLL parameters in a unified manner is proposed. The neural network generates intermediate design variables, which are evaluated through a fully differentiable analytical model composed solely of circuit equations. By eliminating iterative circuit simulations during training, the proposed approach enables rapid, end-to-end optimization while preserving physical consistency and system-level accuracy.

Keywords: Neuromorphic Circuits and Systems
Abstract: Abstract—This paper introduces a highly area- and energy efficient mixed-signal CMOS implementation of a synapse for spiking neural networks (SNNs). The proposed synapse architecture supports spike-timing dependent plasticity (STDP) learning rules within a compact silicon footprint of 172 µm² and an energy consumption of 10.03 fJ/spike. By leveraging mixed-signal design techniques, the architecture capitalizes on relaxed matching and noise requirements, enabling scalable and robust analog computing under low signal-to-noise ratio (SNR) conditions. Unlike conventional subthreshold current based implementations, which are typically limited to around 10 dB of dynamic range, the presented approach achieves a significantly broader dynamic range exceeding 60 dB. The STDP learning curve is directly tunable and designed to be process and temperature-invariant, which enhances programmability and robustness across varying chip manufacturing conditions. These features collectively position the proposed structure as a strong candidate for power-constrained, highly parallel neuromorphic computing platforms. Index Terms—Neuromorphic Computing, Dynamic Range, STDP

Keywords: Hardware-Software Co-Design, Embedded Processors and Controllers, AI Digital Hardware, Accelerators, and Circuits
Abstract: While RTL simulation can confirm functional correctness, it cannot fully capture hardware-specific issues that emerge during board-level validation. This paper presents a Pre-Silicon Hardware Testing (PreSiAware) methodology and TinyTapeout design. To reproduce TinyTapeout-style board interaction before fabrication, we developed a cocotb-based Python testbench and adapted it to run through Micropython firmware on a Raspberry Pi Pico 2 (RP2350) with a Terasic DE10-Lite Max 10 FPGA used as a hardware emulation platform. Initial testing exposed hardware-specific issues, including GPIO mapping mismatches, SPI timing problems, and Micropython type errors, which were corrected to achieve a full pass. These results demonstrate the importance of pre-tapeout hardware validation for designs targeting open-source ASIC shuttles. To prove the concept of PreSiAware, it is validated on systolic-array matrix multiplier implemented with a 3 × 3 array, 4-bit data, and SPI-based interfacing, fitting within four Tiny Tapeout tiles.

Keywords: Biomedical Signal/Image Processing, Point-of-Care Biomedical Diagnostics, Other Areas in Biomedical Circuits and Systems
Abstract: This paper proposes a lightweight hybrid framework for brain tumor segmentation in T1-weighted contrast-enhanced MRI (CE-MRI). The method integrates YOLOv11 for tumor localization with Attention U-Net for fine-grained segmentation, where bounding-box information provides explicit spatial guidance. YOLOv11 first predicts tumor bounding boxes for coarse localization. The detected region is then expanded and cropped to form a tumor-centered region of interest (ROI). A bounding-box attention mask is generated in patch space and concatenated with the cropped MRI patch to form a two-channel input, which is processed by an Attention U-Net. The predicted segmentation is finally mapped back to the original image space. By restricting segmentation to ROI patches, the framework reduces background interference and computational cost. The method is evaluated on the Figshare brain MRI dataset using 5-fold cross-validation. Results demonstrate improved performance over full-image and ROI-based baselines, validating the effectiveness of the proposed detection-guided approach.

Keywords: Analog Circuits and Systems, Physical Design, Test, Verifications
Abstract: We present a passive circuit that emulates a memristive element with fractional-order behavior by combining a diode bridge with a fractional-order capacitor ladder. In contrast to the conventional RC circuit, the fractional-order ladder exhibits multiple-time-scale memory and power-law relaxation dynamics. To mitigate truncation effects, we incorporate a compensating resistor-capacitor pair following established design approaches. It is shown that, in the ideal CPE limit, the distributed ladder dynamics can be represented by a fractional-order state description governed by a Caputo derivative of order 0

Keywords: Other Analog/RF Circuits and Systems, Analog, Digital and Mixed Signal Processing, In-Memory Computing Circuits and Systems
Abstract: Conventional digital predistortion (DPD) relies on high-speed observation ADCs, whose sampling rate/power consumption grows with modulation bandwidth. We present a direct-learning DPD architecture that replaces high-speed digitization in the feedback path with an analog margin-processing compute-in memory (MarginCiM) correlator that directly computes gradient-update correlations. The approach is evaluated using the OpenDPDv2 framework. Measured analog-compute outputs are used in the DPD training loop. The measured prototype consumes 0.5 mW in sampling and about 0.17 mW in compute operation at 2 GS/s for 16 9-bit computations of length 512 with 269 ns total sampling and compute time, enabling more than 30× lower feedback-path energy than an ADC-based solution for a 512 sample frame. Using MarginCiM-computed gradients, the DPD improves ACPR from -33 dBc to -43 dBc and EVM from -27.9 dB to -30.8 dB for a 200 MHz 64-QAM OFDM signal at a PA output power of 14.3 dBm.

Keywords: Hardware Security, Secure AI Hardware, Heterogeneous Integration
Abstract: Modern AI accelerators based on chiplet architectures, including AMD MI300, Intel Ponte Vecchio, and NVIDIA Grace Hopper, universally operate under a critical implicit assumption: all co-packaged dies form a trusted computing base. Die-to-die interconnects such as UCIe, BoW, and AIB carry AI model weights, activations, and gradients in plaintext, leaving them exposed to supply-chain-injected hardware Trojans, compromised third-party IP, and side-channel attacks. The UCIe Security Working Group has acknowledged this gap but published no normative solution. This paper presents SCE (Secure Communication Engine), a lightweight hardware-friendly bump-in-the-wire module that adds ChaCha20-Poly1305 authenticated encryption, mutual HMAC-SHA256 challenge-response authentication, and sliding-window replay protection to UCIe Gen 2 die-to-die links. Discrete-event simulation of a 128 GB/s UCIe link under realistic AI tensor-transfer traffic confirms: mean latency overhead of 106% that decreases to 38.8% at P99 through burst amortization; throughput impact below 0.01% for KB-scale tensor transfers that dominate AI communication; and power/area overhead below 0.4%/0.3% of system resources. SCE provides a concrete, reproducible foundation for die-to-die security in multi-vendor AI chiplet platforms.

Keywords: Analog Circuits and Systems, Regulators, References and Reliability Methods, Other Power Circuits and Systems
Abstract: This paper presents a leakage-aware design and optimization of a step-up linear charge pump for ultra-low-power applications. An analytical model is developed to characterize the output resistance and power efficiency across different operating regimes, incorporating switch leakage and parasitic losses of capacitors and switches as major sources of inefficiency. Based on this model, the switching frequency and the switch sizes are chosen to maximize efficiency. Simulation results demonstrate that the proposed approach achieves peak efficiency near the predicted optimal frequency while maintaining the required power density.

Keywords: Wearable Smart Sensor Systems, AI-IoT Systems and Applications, Biomedical Signal/Image Processing
Abstract: Patients performing knee rehabilitation using physiotherapy outside clinical settings have no reliable means of verifying whether their movements meet therapeutic standards. This paper presents a pasteable, skin-mounted sensing system that combines lightweight inertial measurement units (IMUs) with machine learning to monitor rehabilitation exercises in everyday environments. Kinematic signals, including IMU orientation angles, angular velocity, and linear acceleration, are extracted from segmented motion cycles and used as statistical features for movement quality assessment. Random Forest (RF), Gradient Boosting (GB), and Support Vector Machine (SVM) classifiers are evaluated for normal-versus-abnormal execution detection, with Random Forest achieving 98.22% accuracy and 99.97% AUC. When abnormal motion is detected, the system delivers near real-time haptic feedback at the sensor node, which allows immediate self-correction without clinician involvement, offering a usable solution for home and community-based rehabilitation.

Keywords: Analog Circuits and Systems, Quantum Hardware Systems, Other Analog/RF Circuits and Systems
Abstract: Development and calibration of room-temperature microwave control electronics for superconducting qubits is gated by the cooldown time and limited availability of dilution-refrigerator-mounted qubits used as test loads. We present QEMU, a passive PCB-level distributed microwave circuit that emulates the room-temperature signature of a transmon coupled to a readout resonator. QEMU is a distributed version of the standard cQED equivalent circuit that uses an SPDT switch in place of the Josephson element and a shunt hyperabrupt varactor for both continuous frequency tuning and an emulated AC Stark shift via C(V) nonlinearity, so the drive port load-tests the transmit chain while the readout feedline pair load-tests the receive chain. Large-signal simulations on a Rogers RO4350B-class PCB show a principal coupled mode at 6.58 GHz, with loaded Q ≈ 110 and κ/2π ≈ 61 MHz; a state-dependent dispersive shift χeff/2π ≈ 28 MHz; continuous bias tunability of the qubit-resonator frequency over approximately 250 MHz at essentially constant linewidth; and a power-dependent shift fitting fq(P) = f0 − A Plin, with A ≈ 63 kHz/mW, corresponding to a 58 MHz total span over 0–30 dBm. The current baseline operates in the borderline-dispersive regime; reducing Cg by approximately 5× in a follow-up revision would bring χ/2π into the approximately 1 MHz regime typical of real transmons while reducing the power-dependent shift. The design scales naturally to millimeter-wave frequencies for emerging K-band superconducting qubits.

Keywords: Hardware Security, Digital Integrated Circuits
Abstract: Register-transfer level (RTL) hardware obfuscation has emerged as an important approach for protecting integrated circuit intellectual property against reverse engineering and malicious modifications. Prior polymorphic RTL obfuscation techniques primarily focused on introducing ambiguity within datapath operations without explicitly leveraging low-power design methodologies such as clock gating. This paper presents a polymorphic clock-gating methodology for low-power RTL hardware obfuscation using key-controlled polymorphic logic structures embedded within clock-enable circuitry. The proposed approach replaces conventional clock-gating AND/OR/NAND/NOR logic with a compact multifunction polymorphic structure capable of realizing multiple gate functionalities using the same underlying circuit depending on hidden control-gate and polarity-gate key-bit assignments applied to the polymorphic transistors. Different key assignments modify the ON/OFF behavior of the polymorphic transistors, thereby changing the implemented gate functionality. Consequently, incorrect gate-function or key-bit inference alters clock-gating behavior and introduces incorrect sequential functionality within the protected RTL design. Unlike conventional obfuscation approaches that introduce additional locking circuitry, the proposed methodology embeds obfuscation directly within existing clock-gating logic structures. In addition to introducing functional ambiguity for hardware security, the proposed methodology also reduces switching activity through clock gating, thereby lowering dynamic power consumption. The methodology is evaluated using RTL benchmark circuits and compared against an existing polymorphic functional-unit-based obfuscation framework in terms of power and area characteristics.