Keywords: Regulators, References and Reliability Methods, Other Power Circuits and Systems, Smart Power Management for High-Performance Cloud and AI Data Centers
Abstract: This paper investigates the use of machine learn- ing to estimate the duty cycle of a pulse-width modulated (PWM) signal based on a set of inputs. A switch-mode DC- DC buck converter power supply was used to generate the inputs to the algorithm. Replacing traditional controllers such as proportional-integral (PI) controllers with machine learning controllers can yield gains in real-time control system accuracy and precision. The results demonstrate the machine learning controller’s effectiveness and accuracy. The results highlighted the importance of optimizing the model to be implemented in a practical application.

Keywords: Other AI and Edge Topics
Abstract: Accurate and reliable medical image segmentation is fundamental to modern clinical diagnosis, treatment planning, and disease monitoring. It remains challenging due to organ shape variability, low contrast, long-range dependencies, and limited annotations, particularly across heterogeneous modalities, MSD spleen CT scan and PROMISE12 prostate MRI. To address these challenges, we propose a novel unsupervised transformer-based clustering network, UTC-Net, that minimizes reliance on labeled data without compromising the performance of the network. UTC-Net incorporates transformer-based feature mapping with spectral graph modeling and K-means clustering, supported by pseudo-label refinement, region-affinity modeling, and augmentation-based regularization. Experimental results demonstrate that UTC-Net achieves superior performance on both datasets while requiring significantly fewer parameters than state-of-the-art networks. An ablation study further exhibits the impact of each important module in the proposed UTC-Net network. Our proposed unsupervised segmentation scheme also demonstrates strong adaptability across modalities and annotation, offering a promising direction for a scalable, lightweight, and annotation-free medical image segmentation scheme.

Keywords: AI Digital Hardware, Accelerators, and Circuits, Machine Learning at the Edge, AI-IoT Systems and Applications
Abstract: This paper presents a modular C-based neural network training framework, engineered for FPGA oriented development and High-Level Synthesis (HLS) workflows. While prior research focused on speculative backpropagation as an isolated optimization technique, this work re-frames it as a selectable training mode within a broader, hardware-conscious architecture that supports configurable model construction, deterministic initialization, and repeatable benchmarking. The framework utilizes static-memory data structures, JSON-defined model configurations, and explicit control flow to address the gap between high-level machine learning stacks and the resource-constrained environments of programmable logic deployment. Functional validation was performed using the XOR benchmark and a Driver Drowsiness Detection (DDD) dataset. These experiments confirmed that the framework correctly executes forward and backward propagation and parameter updates for both standard stochastic gradient descent (SGD) and a one-step delayed speculative schedule across varying input dimensions. The central contribution is a stable, documented software foundation that allows future researchers to implement, compare, and isolate compute kernels for hardware acceleration while maintaining a portable software reference. This research enables AI applications on the IoT edge.

Keywords: Sensor Fusion, Internet of Things (IoT) Theory and Systems, Technologies for Smart Sensors
Abstract: The Athena Project is a multi-year multi-discipline project developing a full-stack co-design across scale for personal wearable multi-molecule sensors. The Athena Project’s solutions serve individuals focusing on their own metabolic health through the wearing of these sensors. With advanced multi-molecule sensors and the fusion of machine learning and state-space models, multi-agent embedded solutions will open up a new level of personalized support for a broad spectrum of metabolic illnesses. The team members of the Athena Project include undergraduate and graduate students and key mentors from academia and industry.

Keywords: Electronic/Photonic Integration, Visible/Near-IR/IR Integrated Photonics, Analog Circuits and Systems
Abstract: High-speed electro-optic analog-to-digital converters (eoADCs) are critical for next-generation mixed-signal systems that require ultra-fast data conversion, leveraging the inherent advantages of photonics such as length-independent impedance and high-speed light propagation. We present a novel 1-hot encoded eoADC architecture that utilizes fabrication-compatible photonic components including microring resonators and photodiodes to perform analog voltage quantization and thresholding in the optical domain, effectively addressing the speed limitations of traditional electronic systems. A comprehensive analysis is conducted across a broad design space, encompassing device-, circuit-, and technology-level parameters to optimize both energy efficiency and performance. The architecture supports seamless integration with electronic subsystems via digital bitstream outputs and is highly scalable for mass production using standard silicon photonics foundry processes. Our implemented design, validated using commercial GlobalFoundries' 45CLO process node, achieves 4-bit resolution at 7.5 GS/s with an energy consumption of 4.1 pJ per conversion offering a compelling solution for high-performance computing systems.

Keywords: Converters, ADC, DAC and others
Abstract: Random mismatch in resistor networks is one of the major sources of errors that limit the accuracy of R-2R DACs. This paper proposes an auxiliary-DAC-assisted bit-by-bit calibration technique for a 16-bit R-2R DAC. It achieves high matching accuracy by measuring the weight error of the higher 12 bits and utilizing an auxiliary DAC with 3 fractional bits and 11 integer bits to compensate for it. A MATLAB behavioral model is built and a transistor-level circuit is designed in a 0.18-μm CMOS technology to verify the proposed calibration. Post-layout simulation results show that the calibrated differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.18 LSB and 0.22 LSB, respectively.

Keywords: Converters, ADC, DAC and others
Abstract: This paper presents a novel systematic methodology for the synthesis of the Loop Filters (LFs) in Band-Pass (BP) Delta-Sigma Modulators (∆ΣMs) based on N-Path Filters (NPFs). Based on a linear time-domain transformation, the proposed method transform the problem of synthesizing the LFs of BP ∆ΣMs into a problem of synthesizing the LFs of conventional Continuous-Time (CT) Low-Pass (LP) ∆ΣMs. In this way, the complicated mixing effect caused by the linear periodically time-varying nature of NPFs in the frequency domain is avoided, thus resulting in a more efficient and simple synthesis method as compared to prior art. Moreover, well-known LF synthesis techniques for CT ∆ΣMs can be adopted, thus taking advantage of the know-how of conventional CT ∆ΣMs. A two-stage NPF-based BP ∆ΣM is synthesized using the proposed methodology, demonstrating correct simulation results as predicted by the presented theory.

Keywords: Converters, ADC, DAC and others
Abstract: This paper presents a comparative analysis of resonator circuit techniques for continuous-time bandpass ΔΣ modulators (CT-BPΔΣMs), which are key enablers of direct radio-frequency (RF) and intermediate-frequency (IF) digitization in software-defined radio (SDR) systems. Four representative topologies are examined: dual op-amp active-RC, single op-amp active-RC, Gm-LC, and N-path-filter-based structures. The design trade-offs of each approach are evaluated in terms of center-frequency scalability, quality factor (Q), power efficiency, and sensitivity to process, voltage, and temperature (PVT) variations. The comparison highlights the relative suitability of each topology across different frequency regimes, ranging from IF to multi-GHz RF operation. Based on this analysis, practical design guidelines are derived to support the selection of resonator architectures for digitizers targeting next-generation SDR and cognitive radio receivers.

Keywords: Quantum Architecture and Design, Quantum Hardware Systems
Abstract: Current era quantum computers continue to grow in both capability and capacity. Despite these advancements, errors induced by environmental noise severely limit practical applicability. Current research into error mitigation and correction to bridge the gap between current-era quantum computers and the execution of noise-sensitive workloads. These methods have significant performance and resource overheads, thereby greatly limiting the real-world benefits of their use. Circuit replication, as a naive form of error mitigation, is not new and has largely been ignored given the resource constraints of current quantum hardware. However, its simplicity is attractive as a means to supplement modern methods, reducing the overall performance overhead while still preserving error-mitigation capabilities. In this paper, we profile the effects of simple circuit replication under real-world noise profiles to better establish replication's limits as a supplemental mitigation strategy. Quantum Approximate Optimization Algorithm (QAOA) for the Maxcut problem is explored for the analysis. For small graphs, we found that the average inference strength decreases by approximately 21.8% while the average standard deviation decreases by 108.8% compared to 6 replicates. For larger graphs, inference strength decreases by 35.4% while the average standard deviation decreased only 20.5%. Fewer replications did not affect smaller graphs, but degraded inference strength, with comparable benefits to standard deviation in larger graphs. These results show that replication has potential uses as a supplemental mitigation strategy for large-depth, highly variable workloads.

Keywords: Signal Processing Theory and Methods, Adaptive Signal Processing with Deep Learning, Other Signal and Image Processing
Abstract: High-dimensional feature representations are widely used in machine learning-based cyberattack detection systems. However, they increase computational complexity and may hinder deployment in resource-constrained environments. In this paper, we investigate feature compression techniques for cyberattack classification by comparing two dimensionality reduction approaches: Principal Component Analysis (PCA) and Linear Predictive Coding (LPC). Compressed feature representations with varying dimensionalities are generated and evaluated across several classification models. Experimental analysis demonstrates that PCA preserves classification performance even under aggressive compression. On the other hand, LPC provides competitive predictive representations with slightly larger performance degradation. The results show that substantial reductions in feature dimensionality can be achieved with minimal impact on classification accuracy, highlighting the potential of lightweight feature compression for efficient cybersecurity analytics.

Keywords: Hardware Security, Physical Design, Test, Verifications
Abstract: This paper presents a heuristic strategy for port selection in PCB Trojan detection based on one-port Vector Network Analyzer (VNA) measurements. While prior work has demonstrated the promise of using measured S11 responses to characterize PCB anomalies, port selection is often not discussed systematically. To address this practical gap, this study introduces a heuristic strategy for selecting electrically meaningful probe locations by prioritizing structurally important and highly observable nets that are more likely to capture changes caused by malicious modifications. The method is evaluated on CIAA-Z3R0 boards using measured S11 responses from multiple genuine (golden) and compromised (Trojan) inserted PCBs. Experimental results show that the selected ports provide clear separation between golden and Trojan boards, while golden boards remain relatively consistent and establish a stable baseline. The results suggest that effective PCB Trojan detection depends not only on the measured S-parameter response, but also on principled port selection, making port selection a key step toward practical and reproducible S11 based board integrity assessment.

Keywords: Hardware Security
Abstract: Post-quantum cryptography (PQC) schemes such as the NIST-standardized ML-KEM (CRYSTALS-Kyber) are entering deployment, yet their resilience to side-channel attacks (SCAs) remains insufficiently understood. We study a realistic textit{keyless} attack on ML-KEM's pointwise multiplication: a leakage model trained only on a disjoint known-key set recovers each target's secret by ranking candidate coefficients without ever using its key, relying solely on the public ciphertext r and the traces. On low-noise simulated traces and real CW305 FPGA measurements, we recover the NTT-domain coefficients of s_1 and benchmark CPA, a 1-D CNN, and a compact hybrid (RegNet) against our textbf{texttt{Distill-and-Rank}} framework, which pairs PatchSCA-Lite, a lightweight patch-based Transformer (153k parameters, sim2~ms/trace)---with EMA self-distillation, correlation ranking, and keyless confidence measures (margin, bootstrap stability). On low-noise traces all learned models beat CPA (25 traces to disclosure); the compact hybrid needs the fewest (12) and PatchSCA-Lite 17, with EMA distillation essential for the Transformer to converge. Under high noise and on real hardware, learned models degrade sharply: the compact hybrid gives the best efficiency--robustness tradeoff, while pure attention collapses where low SNR and scale mismatch dominate. Standardized PQC implementations remain vulnerable to leakage, and lightweight hybrid models are the more practical choice for keyless SCA.

Keywords: Hardware Security
Abstract: Fault injection attacks on the CRYSTALS-Kyber Number Theoretic Transform (NTT) exploit the recursive structure of the butterfly pipeline to corrupt polynomial computations and recover secret keys via Differential Fault Analysis (DFA). Existing countermeasures protect the entire datapath uniformly, imposing area and power overheads that are prohibitive for resource-constrained deployments. This work presents ADAPT, a stage-aware parity-based architecture that characterizes how transient faults propagate through the Kyber NTT pipeline and exploits the characterization to secure against Differential Fault Analysis with minimal hardware overhead. The architecture provides robust fault detection by utilizing 12 LUTs and 13 flip-flops(FFs), while avoiding the heavy resource requirements typical of Dual Modular Redundancy (DMR). The design implemented on a Xilinx Artix-7 FPGA, serves as an ultra-lightweight solution for CRYSTALS-Kyber NTT pipelines, maintaining zero negative slack and a minimal 0.02% resource footprint.

Keywords: Human/brain-Machine Interfaces, Biomedical Signal/Image Processing, Other Areas in Biomedical Circuits and Systems
Abstract: This paper presents the design and full-wave electromagnetic simulation of a compact normal-mode helical antenna intended for repeated electromagnetic field stimulation (REMFS) in Alzheimer's disease therapy. The antenna is proposed as a simpler and more compact alternative to the previously reported birdcage--meander-line antenna (MLA) system that operated near 64 MHz. The helical radiator is modeled in Ansys HFSS and co-simulated with a single series matching capacitor. The antenna is designed to operate in the normal mode, where all dimensions are much smaller than the free-space wavelength, and is tuned near 58.47 MHz. Simulated results show good matching with return loss near -35 dB, broad normal-mode radiation, and smooth electric, magnetic, and SAR distributions in a coupled head model. These results support the feasibility of compact helical antennas as REMFS applicators for noninvasive Alzheimer's disease treatment.

Keywords: Other Sensory Circuits and Systems, Other Areas in Biomedical Circuits and Systems, Point-of-Care Biomedical Diagnostics
Abstract: This paper presents a novel skin ablation and sensing system that employs 1) irregular heating and cooling intervals generated by a Peltier module for precise tumor ablation and 2) piezoelectric transmitter and receiver elements that provide real-time monitoring of ablation depth, toward a closed-loop operation. Conventional ablation techniques are effective in destroying tumor tissue; however, they often lack precise control over heat penetration depth, leading to collateral damage in surrounding healthy tissue. Moreover, separate sensing systems are generally required to verify ablation depth during treatment. To overcome these limitations, the proposed system is designed to 1) confine the heat generated by the Peltier module within the tumor boundary and 2) integrate a pitch-catch piezoelectric sensing mechanism for real-time ablation depth monitoring. The complete model, including the Peltier module, piezoelectric elements, and multilayer body tissue, was developed and simulated in COMSOL Multiphysics. The results demonstrate controlled heat penetration depths with a precision of 1 mm across different alternating input current frequencies, 0.008-0.1 Hz, and a saturation capability (continuing the procedure does not change the ablation depth). In addition, over 5 dB reduction of the received acoustic power (>50% acoustic pressure reduction) is achieved for a 2 mm ablation depth increment step size.

Keywords: Analog Circuits and Systems, Sensor Interface Circuits and Microsystems, Lab-on-CMOS and Lab-on-Chip
Abstract: This paper presents an integrated system for measuring sulfhemoglobin concentration based on fluorescence. A 0.18um CMOS on-chip photodiode is characterized under controlled illumination using a 460 nm LED source, where the measured photocurrent defines the operating conditions of the readout stage. A two-stage operational amplifier is implemented as a transimpedance amplifier. Simulation results show that the amplifier meets the required gain, stability, and robustness. The proposed architecture is validated through AC analysis, supporting its use in compact fluorescence-based diagnostic platforms. A noise analysis within the 460 nm fluorescence range is also included.

Keywords: Integrated Biomedical Systems, Other Areas in Biomedical Circuits and Systems
Abstract: Mock circulatory loops (MCLs) replicate the pressure and flow conditions of the human circulatory system and serve as test beds for mechanical circulatory support devices such as left ventricular assist devices (LVADs). Current MCLs lack the ability to synchronize control with real-time electrocardiogram (ECG) signals, limiting the evaluation of dynamic and reactive control schemes for LVADs. This work presents a real-time embedded system that integrates ECG acquisition, low-latency R-peak detection, and synchronized control of both an MCL and an LVAD for beat-to-beat LVAD speed modulation and ventricular actuation. The system achieves a mean end-to-end synchronization latency of 16.8 ms, enabling alignment between electrical activation and mechanical response within a cardiac cycle. Multiple ECG-synchronized LVAD speed modulation schemes are evaluated on a single-chamber MCL, demonstrating measurable hemodynamic effects, including changes in pulse pressure, aortic pressure waveforms, and pressure-volume loops. The proposed system provides a physiologically driven platform for evaluating real-time control strategies for next-generation rotary LVADs.

Keywords: Integrated Biomedical Systems, Biomedical Signal/Image Processing, Other Areas in Biomedical Circuits and Systems
Abstract: We demonstrate an early-stage prototype and initial characterization of a system for tracking eye movement and pupils through closed eyelids to enhance sleep studies. Currently, typical sleep studies use electrodes applied to the scalp and body to track sleep, breathing, cardio-respiratory activity, gross motor movement, and neural activity. We aim to develop technology to track pupil movement and pupil dilation through closed eyelids using infrared light and a augmented sleeping mask to avoid disrupting sleep. This work includes a crude initial wearable device and exploration of the concept with LEDs (light-emitting diodes), along with automated detection of the pupil from images of the eye. Furthermore, we investigated the limits allowed for safe illumination through the temple to ensure no damage results from the use of this approach.

Keywords: Biomedical Signal/Image Processing, Adaptive Signal Processing with Deep Learning, Wearable Smart Sensor Systems
Abstract: Interictal epileptiform discharges (IEDs) are key biomarkers for epilepsy, but their brief duration, morphological variability, and overlap with background electroencephalography (EEG) signals make automated detection challenging. Most existing EEG analysis systems perform only binary or single‑event detection, limiting clinical and real-time applicability. This work presents a system-oriented deep learning framework for five‑class EEG classification: Normal, Delta‑Slow‑Waves, Spike‑Wave, Sharp‑and‑Slow‑Waves, and Poly‑Spikes. High‑resolution Continuous Wavelet Transform scalograms were generated from segmented EEG windows, and a fine‑tuned VGG16 model was trained on 1.6 million images with targeted data augmentation to address class imbalance. Evaluation on unseen EEG recordings achieved 77% accuracy, 74% macro recall, and a macro F1‑score of 0.61, demonstrating robust multi‑class performance despite rare events. The framework preserves both high‑ and low‑frequency EEG features and achieves a system latency of 42.7 ms per window, enabling reliable real‑time event‑level analysis for wearable and embedded platforms. To our knowledge, this is among the first system‑level frameworks for real‑time five‑class IED detection, providing clinically meaningful, scalable, and automated EEG interpretation for diagnostic support, seizure localization, and continuous monitoring.

Keywords: Biomedical Signal/Image Processing, Adaptive Signal Processing with Deep Learning, Wearable Smart Sensor Systems
Abstract: Cardiovascular diseases remain a leading global cause of mortality, making timely and reliable arrhythmia detection essential. This paper presents a lightweight and interpretable framework for four‑class ECG arrhythmia classification using fiducial P–QRS–T morphological and temporal features extracted from a unified PhysioNet dataset integrating MIT‑BIH Arrhythmia (MITDB), Creighton University Ventricular Tachyarrhythmia (CUDB), and Malignant Ventricular Ectopy (VFDB) databases. After correlation‑based redundancy removal and LSVM weight‑rank filtering, six optimal features were used to train a linear‑kernel LSVM within a one‑vs‑all multi‑class design. Using stratified fivefold cross‑validation, the model achieved 85% accuracy with high sensitivity to life‑threatening arrhythmias (VF: 96.9%, VT: 96.7%) and strong performance on Normal (96.3%) and Other rhythms (82.2%). With a model size of only 1.74 MB, power consumption of 12.73 W, and an inference throughput exceeding 143,000 samples per second, the proposed framework offers a transparent, low‑computational‑cost alternative to deep learning. Its efficiency and interpretability make it suitable for real‑time, wearable, and embedded ECG monitoring applications.

Keywords: Biomedical Signal/Image Processing, Wearable Smart Sensor Systems, Signal Processing Theory and Methods
Abstract: The noninvasive extraction of the fetal Electrocardiogram (ECG) remains a challenging signal processing problem due to the dominance of the maternal ECG and the presence of significant noise in abdominal recordings. Many existing methods rely on heavy computational algorithms or multichannel ECG recordings, to separate fetal ECG without maternal interference. This work presents a low-complexity fetal ECG extraction method that combines Independent Component Analysis (ICA) with Fast Transversal Filter (FTF) based reconstruction to suppress maternal interference. Unlike existing approaches, the proposed method requires no external reference signals-such as maternal thoracic or fetal scalp ECG and operates solely on abdominal recordings. Experimental results demonstrate that the FTF reconstruction improves maternal ECG suppression, while maintaining its effectiveness under minimal channel configurations and robustness across normal and arrhythmic fetal rhythms.

Keywords: Wearable Smart Sensor Systems, Integrated Biomedical Systems, Bio-signal Amplifiers
Abstract: This work presents an ultra‑low‑power system‑on‑chip (SoC) design for real‑time stress and anxiety monitoring. The analog front‑end (AFE) incorporates a fully digital DC‑servo loop (D²SL) for electrode‑offset cancellation, achieving a 40% reduction in area and a 35% decrease in settling time compared to conventional analog‑DSL implementations. The back‑end integrates a lightweight shallow neural network (SNN) classifier that directly processes features extracted from two EEG channels, eliminating the need for energy‑intensive off‑chip computation. Designed in a 0.18 µm CMOS process, the proposed SoC achieves an estimated energy consumption of 5.82 µJ per classification while maintaining an accuracy of 88.5% for four‑level stress and anxiety detection, demonstrating strong potential for long‑term wearable applications.

Keywords: In-Memory Computing Circuits and Systems, Emerging Memory and Memristor, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: Resistive RAM (RRAM) crossbars enable in-memory analog matrix–vector multiplication (MVM). However, practical devices exhibit strongly nonlinear current–voltage (I–V) characteristics that degrade the accuracy of conventional voltage-amplitude encoding. This work evaluates a special case of Stream Computing called Asynchronous Stream Computing (ASC) as a circuit-level approach to mitigate this nonlinearity in RRAM-based compute-in-memory (CiM). ASC encodes inputs in the time domain as the duty cycle of constant-amplitude 1-bit Σ∆ streams, so each RRAM cell operates at a fixed Read bias, Vref, and device nonlinearity no longer directly distorts the output current. Circuit-level simulations using the Stanford Verilog-A RRAM model in Cadence Virtuoso (65 nm PDK) compare conventional analog CiM and ASC-CiM under identical device parameters. ASC reduces the maximum relative error for single cells from 25.41% to 0.94% in high-resistance state (HRS) and from 25.57% to 3.96% in low-resistance state (LRS). For 4 × 1, 8 × 1, and 16 × 1 crossbars, ASC lowers the mean full-scale normalized MVM error from 5.76%–10.1% to 0.0405%–0.0260%, corresponding to up to 387× improvement. These results indicate that ASC substantially reduces nonlinearity-induced MVM error in the evaluated RRAM CiM configurations and offers a tunable accuracy–latency tradeoff via the accumulation window Tacc.

Keywords: In-Memory Computing Circuits and Systems, Neuromorphic Circuits and Systems, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: This paper proposes a novel compute-in-memory architecture comprising multi-valued memory units using binary nonvolatile memory devices (NVMs) for brainmorphic circuits. The proposed architecture employs parallel-connected binary nonvolatile memory devices with thermometer-code representation to mitigate the impact of write errors while enabling addition and subtraction of memory values. The feedback write scheme conducts addition and subtraction of memory values on-chip across an array of multi-valued memory units. In this paper, we consider the implementation of voltage-controlled MRAM (VC-MRAM), which offers high endurance and low-voltage operation, making it suitable for brainmorphic hardware.  To verify the circuit operation, we fabricated a CMOS-integrated test chip. This test consists of a single memory unit and a feedback write circuit, where the VC-MRAM devices were replaced with NMOS pseudo-resistive transistors to emulate NVM resistance states.Measurements showed less than 5% error compared to SPICE simulations, confirming accurate memory-to-PWM conversion. Numerical analysis further demonstrated an 87%–95% discrimination probability under 5% resistance variation. These results show the suitability of the architecture for multi-valued weight updates in robust brainmorphic systems.

Keywords: Other AI and Edge Topics, AI-IoT Systems and Applications
Abstract: This paper presents an error-tolerant and energy-efficient neural network (NN) hardware architecture utilizing a unitary-weight (Uw) representation. Reducing the write energy of nonvolatile memories like STT-MRAM is critical for edge devices, but their stochastic switching necessitates long, energy-intensive write pulses. To overcome this challenge, we exploit the inherent error tolerance of NNs by permitting a certain level of bit errors. Specifically, we employ the Uw representation, where all bits have identical weights. The mechanism of its high bit-error tolerance is analytically clarified using the effective number of bits. The analysis demonstrates that the normalized mean squared error (MSE) in Uw decreases as the bit width increases, unlike conventional fixed-point representations where it remains constant. Furthermore, we design and evaluate a Uw arithmetic-based convolution processing architecture through logic synthesis in a 28-nm CMOS process. The results demonstrate that compared to an Fxp4 baseline, the proposed architecture improves the acceptable error rate from 4.5% to 7.0%, achieving 84% and 62% reductions in memory and total energy consumption, respectively. This highly robust and energy-efficient operation proves the efficacy of Uw for NN hardware using stochastic nonvolatile memory.

Keywords: In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Neuromorphic Circuits and Systems
Abstract: Current-domain compute-in-memory (CIM) architectures offer a promising pathway to reduce data movement and eliminate costly data conversion overheads in edge AI systems. However, conventional resistive crossbar implementations rely heavily on peripheral circuits such as analog-to-digital converters (ADCs), which dominate system energy and latency. This work presents a fully current-domain CIM architecture that performs matrix–vector multiplication (MVM) through direct summation of weighted input currents using current mirrors, eliminating the need for intermediate voltage domain conversion and ADC-based readout. Synaptic weights are implemented using a two-ReRAM voltage-divider structure that improves robustness to device variability by ensuring rail-to-rail switching behavior. An integrated current-domain non-linear activation stage suppresses leakage and background light currents. Circuit-level simulations demonstrate 9.6× improvement in energy efficiency and 8.3× reduction in latency compared to an ADC-based baseline. The proposed architecture enables scalable and energy-efficient current-domain in-memory computing for edge AI applications.

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: A ring amplifier based switched-capacitor digital-to-analog converter (DAC) for charge-domain compute-in-memory (CIM) arrays is presented in a 65-nm CMOS process. The proposed architecture employs a dual coarse/fine output stage with Monticelli and diode biasing, enabling fast slewing and stable operation across a wide data-dependent capacitive loads ranging from 50 to 500 fF, while using minimum-size transistors. The ringamp structure provides near rail-to-rail slewing with low quiescent current, improving energy efficiency for CIM workloads. Simulations show an average conversion energy of 140 fJ and a maximum operating frequency of 95 MHz. An energy figure-of-merit shows that the proposed DAC breaks the analytical energy lower-bound of the resistive DAC commonly used in charge-based CIMs, offering a 58% reduction in conversion energy in the average case, and a 20% reduction in the worst case.

Keywords: Other Sensory Circuits and Systems
Abstract: Hyperspectral imaging has become increasingly useful in recent years. This work presents a two-dimensional detector array based on single-photon avalanche diode (SPAD) pixels for hyperspectral imaging across the near-ultraviolet (NUV), visible, and near-infrared (NIR) bands. The array includes 128 macro-pixels (8×16), and each macro-pixel is divided into four sub-pixels: two for NIR imaging and two for NUV imaging. Using a dedicated foundry process, multiple SPAD types can be integrated and interfaced with the same active quenching and recharge (AQR) circuit and digital counter, enabling hyperspectral operation with minimal circuit changes. The pixel circuit combines an AQR block with a mask function that speeds up quenching and recharge, and it disables the recharge path during idle periods to reduce power consumption. By sharing the high-voltage guard ring and rearranging the counter and quenching circuitry, the proposed imager increases the pixel fill factor (FF) from 6% to 21%, which corresponds to a 3.5× improvement.

Keywords: Sensor Interface Circuits and Microsystems, Other Sensory Circuits and Systems
Abstract: This work presents an in-pixel active quench and reset circuit (AQRC) that leverages a regenerative positive feedback for fast quenching of a single photon avalanche diode (SPAD). Implemented in a 40 nm CMOS process, the proposed circuit detects a photon event within 410 ps and rapidly quenches the SPAD to flush out the trapped carriers, thereby reducing the afterpulsing probability and dark count rate. The circuit exploits both thin-oxide and thick-oxide transistors, enabling operation across a supply range of 1 V to 2.5 V. Post-layout simulations using extracted SPAD device model demonstrate photon detection rates upto 500 Mcps with an average power consumption of 44.34 uW at 100 Mcps.

Keywords: Other Sensory Circuits and Systems, Other Wireless and Communications Topics
Abstract: Direct time of flight (dToF) measurements are susceptible to errors because of system-level and circuit-level timing jitter. In addition, device-level uncertainty stemming from the dark noise of single-photon avalanche diode (SPAD) contributes to the aggregated error. We demonstrate that perimeter gating can help reduce the device-level detection inaccuracy for SPAD devices by reducing the dark noise probability. Specifically, in this work, we developed a general framework to accurately estimate the dToF jitter stemming from different source levels and analyzed a counter-based time to digital converter (TDC) circuit. We have also measured dToF using a perimeter-gated SPAD (pg-SPAD) detector fabricated in a 0.35 μm standard CMOS process. Experimental results show that pg-SPADs can improve measurement accuracy in both free-running and time-gated operations.

Keywords: Other Sensory Circuits and Systems, Other Wireless and Communications Topics
Abstract: Perimeter-gated single-photon avalanche diodes (pg-SPADs) are known for their dynamic dark noise modulation capabilities. They are reported to trade noise for photon sensitivity under continuous illumination. However, the implications of this trade-off have not heretofore been studied with pulsed optical systems. This work bridges this gap. We demonstrate that pg-SPADs fabricated in a 0.35 μm standard CMOS process trade-off pulse detection efficiency for a reduction in the the spread of spurious events within a burst window. Consequently, herein, we propose guidelines for the optimal use of pg-SPADs in pulsed LIDAR applications in view of the observed trade-off.

Keywords: Lab-on-CMOS and Lab-on-Chip, Other Beyond CMOS Topics
Abstract: Area utilization is the primary design constraint for microfluidic devices. For stereolithography 3D printed devices, the optical print area defines maximum available area. To design chips with larger component counts, we propose partitioning the design across multiple chiplets, which can then be assembled together to form a distributed chip. Because the same manufacturing area limitations apply to manufacturing an interposer, we propose a peer-to-peer connection topology where chiplets are directly connected to neighboring chiplets. We propose an algorithm for partitioning the circuit across a target chiplet topology, and routing the interconnections between chiplets. We also propose a set of target topologies and demonstrate the methodology on a set of microfluidic benchmark devices. Benchmark circuits up to eight times larger than current standard fluidic designs were successfully generated.

Keywords: System on a Chip (SOC) and Network on a Chip (NOC), Communications Systems and Control, Internet of Things (IoT) Theory and Systems
Abstract: Wearable E-textiles rely on embedded wireline networks to collect data and enable scalable, physically distributed computation within fabrics. Reliability remains challenging due to the fragility of conductive fibers and the interconnect limitations imposed by mm-scale chiplets. As chiplet areas shrink below 1 mm², the cost of redundancy becomes increasingly prohibitive. Existing systems improve robustness through error-detecting codes, redundant wires, or packet rerouting, but these approaches incur area and latency overheads that are poorly suited for resource-constrained wearable networks. This work proposes and experimentally validates fallback protocols in silicon. Fallback protocols are an adaptive link-level reconfiguration strategy wherein links autonomously transition to communicate with fewer wires following a fault. A Python-based fault-tolerance model evaluates reliability and worst-case latency across network topologies, link configurations, and wire failure rates. Under uniform failure conditions, torus networks supporting three fallback protocols improve resilience by 5.7× compared to networks without fallback, consuming as little as 0.009 mm^2 of extra active on-chip area. Latency is influenced by topology, wire count, and failure rate. At a 60% wire failure rate, the worst-case path in a 4-wire mesh is 17% slower than in a 3-wire torus. At a 20% wire failure rate, the 4-wire mesh achieves a 2× reduction in worst-case latency relative to the torus. Results demonstrate that fallback protocols enable reliable, area-efficient E-textile network design and provide system-level guidelines for wearable health and interactive platforms.

Keywords: Analog Circuits and Systems, Mixed-Signal RF and Baseline Circuits, Analog, Digital and Mixed Signal Processing
Abstract: Wideband sensor arrays require multi-beam beamforming while maintaining low size, weight, and power (SWaP). This paper presents a mixed-signal beamforming chiplet pair that combines analog approximate discrete Fourier transform (a-DFT) processing with high-speed data conversion and a wired digital link. The transmit chiplet accepts eight baseband inputs and performs current-mode 8-point a-DFT beamforming using multiplierless coefficients {0,+/-1,+/-2}. The beam currents are converted to voltages and digitized by a 4times time-interleaved 8-bit successive-approximation-register (SAR) ADC at 1.0 GS/s. The digitized beams are serialized and transmitted over dual 10 Gb/s differential links using 8b/10b encoding. A companion receive chiplet performs clock and data recovery (CDR), adaptive equalization, and line decoding. Both chiplets are designed in 28-nm CMOS and support 500 MHz instantaneous bandwidth. Simulations indicate >50 dB SNDR across the analog path, 45.7 dB ADC SNDR (7.3 ENOB), and reliable dual 10 Gb/s operation over PCB channels while consuming 197.1 mW total.

Keywords: Neural Networks and Fuzzy Logic, Signal Processing Theory and Methods, Heterogeneous Integration
Abstract: Chiplet-based architectures are increasingly adopted in modern semiconductor systems to improve scalability, performance, and design flexibility through heterogeneous integration. Reliable communication between chiplets depends on high-quality interconnect waveforms, which may be degraded by noise, amplitude distortion, phase variation, and other signal integrity impairments. Early detection of such faults is essential for ensuring reliable system operation and reducing validation effort.

This paper presents a deep learning-based approach for automated fault detection in chiplet interconnect signals using synthetic waveform data. Nominal sinusoidal waveforms and controlled distortions, including additive Gaussian noise, amplitude scaling, and phase shifts, are used to evaluate the feasibility of deep learning-based fault detection. Two neural network architectures are investigated: a multilayer perceptron (MLP) and a one-dimensional convolutional neural network (1D CNN).

Experimental results show that both models classify normal and faulty waveforms with high accuracy. The MLP achieves 94% classification accuracy, while the CNN achieves 100% accuracy on the synthetic dataset and converges faster by effectively capturing localized waveform features. Confusion matrix analysis further indicates that the CNN reduces misclassification errors and improves robustness to signal distortions.

These results demonstrate the feasibility of applying deep learning to waveform-level fault detection in chiplet interconnects. Although evaluated using synthetic waveform data, the proposed framework establishes a foundation for future validation using more realistic channel models and measurement-based datasets, with the potential to improve validation efficiency and reduce reliance on manual waveform inspection.

Keywords: Quantum Hardware Systems, Quantum Architecture and Design, Hardware Security
Abstract: As satellite communication infrastructure shifts toward a post-quantum-secure paradigm, the integration of NIST Round 4 candidates, such as Hamming Quasi-Cyclic (HQC) code-based cryptography, enables secure and efficient satellite uplink communication under stringent power and latency constraints. However, the migration of HQC to resource-constrained devices, such as the STM32, introduces physical-level vulnerabilities to side channel attacks (SCA). This paper proposes a side-channel-resilient implementation of the HQC-128 polynomial multiplication for ARM Cortex-M4-based satellite uplink systems, specifically hardened against Simple Power Analysis (SPA) attacks. To mitigate secret key leakage, we implement a hybrid countermeasure strategy that combines stochastic temporal jitter and power masking via a post-compilation assembly-level patching utility. Experimental results demonstrate that the proposed countermeasure introduces a manageable memory overhead of 12.0% with no impact on RAM utilization and execution efficiency. Most significantly, the defense reduces the Bit Success Rate (BSR) to the theoretical minimum of 50.00% and increases the Hamming Distance to 32 bits, making key recovery statistically equivalent to random guessing under SPA attacks. These findings suggest that assembly-level hybrid hardening provides an effective and low-cost solution to secure the next generation of post-quantum satellite uplinks on ARM Cortex-M4 platforms against physical side-channel adversaries.

Keywords: Hardware Security, Secure AI Hardware, Internet of Things (IoT) Theory and Systems
Abstract: The widespread deployment of Internet of things (IoT) devices across diverse applications has increased the need for secure authentication in resource-constrained environments. Physical unclonable functions (PUFs) exploit intrinsic manufacturing variations to generate unique device responses without storing secret credentials. This work presents an area-efficient arbiter PUF design in 28 nm CMOS for IoT authentication. The proposed design is evaluated in terms of timing, area-delay trade-off, and power consumption. Compared to the conventional architecture, it exhibits higher propagation delay and increased per-stage delay contribution under equivalent conditions, reflecting an inherent area-delay trade-off. The design introduces a modest increase in transistor count per stage while maintaining comparable power characteristics. It achieves strong uniqueness (49.41%) and uniformity (49.97%), demonstrating stable statistical behavior. These results indicate suitability for hardware-based authentication in resource-constrained IoT systems.

Keywords: Hardware Security, Internet of Things (IoT) Theory and Systems, Digital Integrated Circuits
Abstract: SRAM power-up states provide low-cost physically unclonable functions (PUFs) on commodity microcontroller units, but response noise can affect authentication repeatability. This work evaluates an ECC-free SRAM-PUF workflow in which each device builds its own golden-bits list directly from its golden-bits file, without assuming preferred bit positions, preferred four-bit groups, or globally shared address sets. A complementary analysis across paired 1000-readout tests investigates whether stable bits exhibit byte-position reliability trends. During enrollment, each device forms a 32-bit challenge-response pair from four fully stable SRAM bytes when available; if fewer than four fully stable bytes are available, the workflow can fall back to selecting reliable stable bits from eight byte addresses. Authentication combines three-readout majority voting with Hamming-distance verification using a fixed 2-bit tolerance over the 32-bit response. Experiments on 40 ATmega32U4 Arduino Micro boards across 1000 readouts achieved a 94.9% reliable-to-stable ratio, with zero false rejects for genuine devices, and zero false accepts for impostors. Although a 32-bit response was used as a lightweight proof of concept for IoT authentication, the proposed approach is readily scalable to longer response lengths.

Keywords: Other Signal and Image Processing
Abstract: This work presents a comparative evaluation of four CMOS compatible analog encryption architectures suitable for resource limited systems. The architectures are evaluated with discrete components and 180 nm CMOS implementations. Chaotic signals from Chua and Lü based systems are used as encryption keys, and the resulting encrypted signals are evaluated using Shannon entropy, autocorrelation, plaintext correlation, and mutual information. The results demonstrate that both the chaotic source and parameters such as resistance and open loop parameters of the opamps influence the overall performance.

Keywords: Analog Circuits and Systems, Other Analog/RF Circuits and Systems, Mixed-Signal RF and Baseline Circuits
Abstract: This paper proposes a novel differential AC-AC charge pump that achieves the highest published voltage gain per capacitor. The voltage gain at each stage follows a Pell-like integer sequence (1, 3, 7, 17, 41, …) defined by a recurrence relation where the gain of any given stage is twice the gain of the immediately preceding stage plus the gain from two stages prior. A 3-stage prototype is fabricated in GF22FDX-SoI. The switches are driven directly from an on-chip dual-transformer-coupled class-D oscillator operating with a power of 665 microwatts at 2.4GHz. Measurements show the 3-stage charge pump achieves a maximum gain of 16.7v/v (98% of the theoretical gain) and a 3dB bandwidth of 13.0kHz. The simulated total output noise of the charge pump alone is 16.7 nano-volts squared.

Keywords: Wireless Charging and Energy Harvesting, Other Power Circuits and Systems
Abstract: This work presents a multi-step switched-capacitor (SC) boost converter that delivers power from a single input source to dual outputs in a time-interleaved manner. The proposed architecture simultaneously enhances power transfer efficiency to both outputs under microwatt-level input power by fully reutilizing the flying capacitor network and minimizing charge redistribution losses through a reconfigurable multi-step charging and discharging strategy. The converter provides a regulated 1.2 V output to power downstream load circuits during one phase and transfers power to a 1.8 V battery during the alternate phase. Implemented in 65 nm CMOS with a total f lying capacitance of 2.2 nF, the proposed converter delivers an output power range of 50 µW to 160 µW from a solar cell input spanning 0.4 V to 1.0 V. It achieves a nearly flat efficiency above 72% across the entire input voltage range, with a peak efficiency of 78.6% to the 1.2 V load and 76.6% to the 1.8 V battery when operated at a 2 MHz switching frequency.

Keywords: Power Management of Electric Vehicles, Analog Circuits and Systems
Abstract: Battery protectors act as the final safety barrier for lithium-ion battery packs, yet state-of-the-art designs cannot break the inherent trade-off among ultra-low power consumption, high-precision monitoring, and fast fault response, and this dilemma has become a critical bottleneck for battery management systems in electric vehicles and energy storage systems. This paper proposes an ultra-low-power, low-fault-delay battery protection circuit for multi-series cell battery management system. The design integrates four synergistic innovations: a zero-quiescent-power gate-boosted high-voltage sampling front-end, a zero-quiescent-power dynamic comparator, a zero-quiescent-power threshold generator, and an op-amp-free switched-capacitor level shifter. The circuit is designed based on a 180nm high-voltage BCD process and supports 16-channel cell monitoring. Simulation results show that it achieves 130nA average operating current, 4nA cell input current, ±5mV sampling accuracy, and 8ms fault response delay, outperforming mainstream commercial solutions.

Keywords: Analog Circuits and Systems, Converters, ADC, DAC and others, Other Power Circuits and Systems
Abstract: Non-overlapping clock signals play a critical role in ensuring efficient and reliable operation of charge pump circuits by preventing short-circuit current paths. This paper presents the design and performance evaluation of a charge pump circuit driven by a recently introduced laddered inverter-based nonoverlapping clock generator. This clocking scheme significantly reduces silicon area compared to conventional non-overlapping clock generators, thereby minimizing the overall footprint of the on-chip charge pump system. A complete chip has been designed, fabricated, and tested using 65 nm CMOS technology. Measurement results confirm that the laddered inverter approach achieves comparable performance in terms of output voltage and efficiency while offering improved area efficiency, making it highly suitable for power- and area-constrained integrated systems.

Keywords: Physical Design, Test, Verifications, Analog Circuits and Systems
Abstract: This work describes the implementation and simulation of single-event latch-up (SEL) models in the Open-Source Circuit Radiation Effects (OSCRE) framework. The framework includes a library of SPICE-compatible radiation simulation cells and a GUI based on open-source EDA tools. The cells can be configured to model SEL for specific test cases at varying levels of complexity. The accuracy of the models is validated through comparison to TCAD simulations. We demonstrate the utility of OSCRE by simulating SEL in a ring oscillator and an op amp. The platform is fully open-source, making it accessible to the circuit design and radiation effects communities.

Keywords: Analog Circuits and Systems, Signal Processing Theory and Methods
Abstract: This paper presents a sensor placement framework for thermal monitoring of analog ICs where device footprints create exclusion zones that prohibit sensor insertion at hotspot locations. Unlike prior methods developed for digital processors that select sensors from discrete candidate grids including hotspot regions, our approach operates in continuous (x, y) coordinates and must extrapolate hotspot temperatures from surrounding sensors. A data pipeline from Cadence Legato electrothermal simulations constructs continuous thermal fields from irregular device-level data via Delaunay triangulation. A constrained random walk optimizes a temperature-weighted dual objective under exclusion zone, die boundary, and inter-sensor spacing constraints. The Calinski-Harabasz criterion provides data-driven guidance for the sensor count. A regionalized initialization strategy ensures that the stochastic optimizer consistently achieves hotspot estimation errors within 2 ◦C across independent runs. With 37 sensors and a single calibration map, Gaussian process regression (GPR) reconstruction reaches 0.74 ◦C maximum hotspot error, improving to 0.41 ◦C at the Calinski-Harabasz recommended 40 sensors. The optimization completes in 6.5 seconds.

Keywords: Digital Integrated Circuits
Abstract: This work addresses a new problem of simultaneous via resizing and in-cell route (i.e., metal segment) relocation on standard cell layouts to enhance the cell delay and signal integrity, which has never been considered in the prior cell generation works. Our method of co-optimizing via resizing and metal segment relocation is general enough to be applied to any of the existing cell layouts with a minimal modification on the in-cell routes. Precisely, we propose a two-step approach to the problem: (Step 1) extracting metal segment scopes and their bundles for metal relocation and (Step 2) simultaneously performing via resizing and metal relocation with the objective of maximizing the total size of the vias on the critical timing paths while satisfying all design rule constraints,formulating it into an SMT (Satisfiability Modulo Theory) problem instance. Through experiments with the cell layouts in ASAP7 PDK as well as produced by the state-of-the-art cell layout generator, it is shown that using our method is able to reduce the cell delay by up to 2.6% while maintaining the same cell area and almost the same in-cell metal usage.

Keywords: Digital Integrated Circuits
Abstract: This paper proposes an efficient multi-row-height standard cell layout generator that overcomes the unacceptable runtimes of prior methods while achieving comparable PPA (performance, power, area) and pin accessibility. Our systematic cell synthesis approach consists of the following steps: (Preprocessing) clustering transistors based on CMOS gate stages; (Step 1) generating multi-row ‘shape’ candidates for each cluster via SMT (Satisfiability Modulo Theories) to minimize area; (Step 2) performing intra-group transistor placement for these candidates using a conventional generator; (Step 3) performing inter-group placement to find an area optimal linear ordering of shapes considering routability, utilizing a fast best-first search; and (Step 4) applying in cell routing via an SMT formulation. Experiments using the ASAP7 PDK (6-routing tracks) demonstrate that our generator achieves an 11∼20× speedup over the state-of-the-art while maintaining comparable layout quality.

Keywords: Digital Integrated Circuits, System on a Chip (SOC) and Network on a Chip (NOC), Hardware-Software Co-Design
Abstract: Singular Value Decomposition (SVD) is an elementary kernel in real-time signal processing, especially in Multiple-Input Multiple-Output (MIMO) communication systems. Conventional hardware implementations of the Brent & Luk Jacobi SVD algorithm are based on iterative CORDIC- based rotation blocks, which are known to have limitations in pipelining due to the dependency between rotation angle generation and matrix updating. In this paper, we propose a decoupled systolic array with an algebraic processing element to eliminate iterative rotation angle calculations through direct fixed-point implementations in DSP slices. A fully pipelined implementation is achieved with an initiation interval of 1. A polymorphic 32-bit fixed-point datapath supports both real and complex inputs and computes the singular values together with the corresponding orthogonal factors U and V without requiring conventional 2N × 2N structural expansion for complex matrices. The architecture also incorporates a permutation network to reduce data-movement overhead and an AXI4-Stream interface with zero padding to support matrices of arbitrary dimensions, including odd sizes. Implemented on a Xilinx Zynq UltraScale+ ZCU104 MPSoC,the design achieves operation at 250 MHz and reduces latency by up to 74.4% on a 20 × 20 matrix, while maintaining constant DSP and BRAM usage across tested matrix sizes.

Keywords: Analog Circuits and Systems, Physical Design, Test, Verifications, Other Analog/RF Circuits and Systems
Abstract: This paper improves upon an existing spectrum-based delay measurement technique. This work proposes a technique in which all the magnitude measurements required to estimate the delay are at the same frequency, allowing the effect of measurement parasitics to be cancelled. The two signals whose phase difference is to be measured are combined so that the new phase-modulated signal produces a spur at one-fourth the input frequency, with spur magnitude proportional to the phase difference. To estimate the effect of parasitics in the measurement setup, the magnitude of the signal at one-fourth the input frequency is measured when the input is divided by four. The proposed method eliminates the effect of frequency-dependent response of the parasitics by combining the above two measurements. Monte Carlo simulations of the proposed method for an input delay of 100ps gives an estimated delay with a mean of 99.9ps and a standard deviation of 0.34ps when simulated with measurement cable lengths of 20cm and 50cm. Monte Carlo simulation results show that the proposed technique improves the estimation error from 7% to 0.1% compared to the existing spectral-analysis-based delay estimation technique.

Keywords: Signal Processing Theory and Methods, Analog, Digital and Mixed Signal Processing, Other Signal and Image Processing
Abstract: Direction-of-arrival (DOA) estimation under low Signal-to-Noise Ratio (SNR) with coherent sources remains a persistent challenge in array signal processing. Classical MUltiple SIgnal Classification (MUSIC) requires eigendecomposition of the sample covariance matrix, an O(M^3) operation that becomes numerically fragile under limited snapshots or high source cor- relation failing correct detection. Therefore, Adaptive Fractional Projection MUSIC (AFPM), a decomposition-free estimator that replaces eigendecomposition with an adaptive, power-iteration- based subspace learning stage is proposed. AFPM combines forward–backward spatial smoothing, difference coarray (DCA) virtual aperture extension, nonlinear magnitude compression, and a self-adjusting fractional power iteration. AFPM offers improved peak sharpness and sidelobe suppression of up to 9.5 dB with an entropy-weighted pseudospectrum. AFPM estimates the DOAs at 70°, 85°, and 130° for a six-element ULA with coherent sources at SNR = 3 dB. At an 8° separation, sub-degree RMSE remains below 1◦ for SNR > −5 dB. The Kintex-7 FPGA results with 128 snapshots reveal a maximum error of 2.0°.

Keywords: Processor and Memory Design and Architectures, Hardware-Software Co-Design, Streaming and Human-Computer Interactions
Abstract: 360° video processing demands high bandwidth, storage, and energy, posing challenges for edge devices such as augmented reality (AR), virtual reality (VR), smart glasses. This work proposes an adaptable, memory-centric architecture that optimizes both pre-encoder buffering and post-decoder storage through region-aware, flexible bit truncation. In the pre-encoder stage, truncating 1 to 6 bits per color channel in non-ROI regions yields 7%–43% read-power reduction. In the post-decoder stage, region-aware heterogeneous truncation across FoV, border, and background areas provides 13%–38% power savings while maintaining high visual quality (≈ 42 dB WS-PSNR) and reducing frame size by up to 50%. The proposed framework leverages application-aware memory optimization to balance energy efficiency and visual quality. The results demonstrate that memory-centric design can significantly reduce power consumption while maintaining perceptual fidelity, enabling scalable and low-power immersive video processing.

Keywords: Sensor Fusion, Physical and Chemical Smart Sensing Systems, Sensor Interface Circuits and Microsystems
Abstract: Simultaneous multi-technique electrochemical sensing enhances multi-analyte detection and improved measurement throughput, but performing parallel measurements in shared electrolytes can introduce electrical crosstalk between sensing cells. This work experimentally investigates how electrochemical cell geometry and measurement instrumentation jointly influence coupling in microfluidic sensing arrays. Measurements performed on a controlled microelectrode platform demonstrate that electrode guarding structures alone are insufficient to suppress interaction during simultaneous measurements. Instead, reliable operation requires coordinated design of both the electrochemical cell and the readout circuitry. These results highlight the importance of system-level co-design when developing miniaturized electrochemical platforms for multi-analyte sensing applications.

Keywords: Physical and Chemical Smart Sensing Systems, Sensor Fusion, Analog Circuits and Systems
Abstract: Voltammetric techniques are central to modern chemical and biosensing applications because they directly translate molecular processes into measurable electrical signals. Many of these applications require different potentiostat topologies to ensure accurate biasing and interference-free measurements. This work presents the Multi-Topology Potentiostat (MTPstat), a programmable PCB potentiostat that supports all three grounded-electrode topologies and a bipotentiostat mode while reducing analog hardware resources by 46%. Electrical characterization demonstrates high linearity and high-resolution current measurements to support a range of testing scenarios. We verify the MTPstat’s operation with two main voltammetric techniques and show strong agreement with commercial benchtop instrumentation, establishing the MTPstat as a high precision, portable, and flexible electrochemical testing instrument at a fraction of the price of commercial devices.

Keywords: Technologies for Smart Sensors, Analog Circuits and Systems, Physical Design, Test, Verifications
Abstract: The rapid growth in industrialization has caused serious levels of contamination with arsenic (As) in industrial effluents, resulting in health hazards such as cardiovascular diseases and different types of cancer. Traditional techniques like ICP-MS (Inductively Coupled Plasma Mass Spectrometry), AAS (Atomic Absorption Spectroscopy), and colorimetric kits are time-consuming and demand skilled personnel. Although nanomaterial-based sensor techniques are sensitive, they are plagued by stability, fouling, and reproducibility problems in wastewater sample. Existing portable electrochemical techniques are also limited. PalmSens SensitSmart and BioLogic SP-300 are limited by the need to manually analyze the voltammogram and Pourbaix diagram, whereas the iQuan system is limited by the need for chemical pretreatment. In this paper, we present SenseM – an autonomous arsenic detection system which works on the basis of Square Wave Anodic Stripping Voltammetry (SWASV). The system consists of a custom-designed analog front end with a potentiostat, a pH sensor, and an ESP32 microcontroller that comes with firmware having optimized parameters for SWASV. The system automatically detects and measures the level of arsenic using an in-built peak detection function with the help of a built-in E-Pourbaix diagram. Our system has shown excellent linearity with 𝑅2 = 0.997 at pH 4.5 and 𝑅2 = 0.998 at pH 9.5. This system enables user-independent, real-time, quick on-site arsenic monitoring in industrial wastewater.

Keywords: Implantable/injectable Systems, Integrated Biomedical Systems, Analog Circuits and Systems
Abstract: This paper presents a wireless battery-free glucose sensing system-on-chip (SoC) for chronic brain monitoring. Implemented in TSMC 65nm CMOS, the implantable SoC integrates a wireless power management unit, a current sensing front end, and a Manchester-coded backscattering uplink. The measured power consumption of the SoC, excluding the LDO, ranges from 2.9 to 3.1uW, while the current-sensing front end achieves an SFDR of 50.9dB in measurements. In vitro wireless glucose measurements show successful sensing of glucose concentration changes, and H2O2 measurements using an in-house-fabricated nanoPt microelectrode array demonstrate the compatibility of the proposed SoC with custom neurochemical electrodes. This work demonstrates a compact wireless battery-free glucose sensing SoC toward miniaturized brain monitoring applications.

Keywords: Physical and Chemical Smart Sensing Systems, Other Areas in Biomedical Circuits and Systems, Other Sensory Circuits and Systems
Abstract: This paper presents the development and characterization of a low-cost, portable electrochemical alcohol sensor system using screen-printed electrodes (SPE) integrated with the LMP91000 potentiostat. The sensor employs carbon-based working and counter electrodes with a silver reference electrode, fabricated using a Voltera V-One printer on fiberglass. Ethanol detection was performed in simulated sweat solutions containing 0.9% saline with ethanol concentrations ranging from 0% to 30%. Cyclic voltammetry (CV) and chronoamperometry (CA) techniques were utilized to characterize the electrochemical response. Results demonstrate concentration-dependent current responses with steady-state currents ranging from approximately 0-2 μA at 0% to 35-40 μA at 30% ethanol concentration, confirming the sensor’s sensitivity to ethanol. The system shows promise as a simple, portable platform for wearable alcohol monitoring applications, though further calibration and optimization are required for quantitative blood alcohol content (BAC) estimation.

Keywords: Other Neural and Neuromorphic Circuits and Systems Topics, Neuromorphic System Algorithms and Applications, Neuromorphic Audio and Video Processing
Abstract: Combining a Dynamic Vision Sensor (DVS) with a Dynamic Neural Field (DNF) algorithm enables fast, reliable motion tracking. The DVS reduces image data, while the DNF ensures robust tracking with memory, even when the target stops and the DVS produces no output. However, traditional DNF models using sigmoidal activation functions struggle with accuracy in the presence of nearby objects, which can be mistaken for the target. To overcome this, we propose an adaptive thresholding technique. Experiments show it reduces average tracking error by 3.28× compared to the sigmoidal approach.

Keywords: Neural Networks and Fuzzy Logic, Machine Learning at the Edge, AI-IoT Systems and Applications
Abstract: Early detection of dental caries on panoramic radiographs is critical for preventive dentistry and effective clinical decision-making. However, manual interpretation of Dental Orthopantomograms (OPG) is time-consuming and prone to inter-observer variability. This study presents an automated cavity detection framework based on the YOLOv8 (You Only Look Once) object detection architecture for precisely localizing dental caries in panoramic X-ray images. The clinically curated Mendeley Dental OPG dataset was preprocessed using Contrast-Limited Adaptive Histogram Equalization (CLAHE) and annotated for single-class cavity detection. Experimental results demonstrate that the YOLOv8s model achieved the best overall performance, with high detection precision, strong sensitivity, an image-level diagnostic accuracy of 95.65%, an F1-score of 96.3%, and a mean Average Precision (mAP@0.5) of 90.1%. The lightweight YOLOv8n model achieved an mAP of 86.7%, enabling efficient real-time inference suitable for resource-constrained screening environments. Model performance was further evaluated using clinically relevant metrics, including sensitivity, specificity, balanced accuracy, and ROC-AUC. These findings demonstrate the effectiveness of YOLO-based deep learning for automated cavity screening in panoramic radiographs. Nevertheless, the limited availability of large-scale expert-annotated datasets remains a key challenge. Future work will focus on expanding dataset diversity, improving annotation quality, and enhancing model robustness for reliable clinical deployment.

Keywords: Image, Video and Multi-Dimensional Signal Processing, Other Signal and Image Processing
Abstract: Traditional autonomous navigation systems often treat vanishing point (VP) estimation as an auxiliary perception constraint or an implicit variable for road modeling. This paper proposes a computationally efficient alternative for low-speed autonomous robots (3--5~mph) by utilizing the VP as a direct geometric control objective. The proposed approach employs a lightweight lane-detection pipeline based on edge extraction and Hough Transform line parameterization, to extract dominant lane boundaries, whose intersection approximates the VP. The VP along with identified lane lines define a triangle, where the angle error is used as the primary setpoint for a proportional controller to maintain lane centering. Experimental results in Gazebo ROS2 environment demonstrate that this approach can compensate for road curvatures and lateral offsets. The system maintained a half lane normalized error of 0.2, demonstrating that VP triangle distortion-based control is a viable, low-latency solution for light autonomous platforms.

Keywords: Machine Learning at the Edge, Other AI and Edge Topics, Image, Video and Multi-Dimensional Signal Processing
Abstract: Galvanometer-scanned FMCW LiDAR produces point clouds whose density falls as r^-3 with range, faster than the r^-2 link-budget SNR attenuation, making sampling sparsity the primary long-range quality constraint. Standard reconstruction algorithms fail at algorithm- and scene-dependent distances, but lack characterization of failure modes under FMCW-specific sparse sampling. We derive Nyquist-based breakdown distances for four algorithms, confirming TV regularization fails at 0.33× its predicted distance due to over-smoothing, while passive interpolants meet or exceed predictions. Exploiting complementary range profiles, we train FMCWDepthNet, a 67.5 K-parameter depthwise-separable encoder-decoder with INT8 quantization-aware training. The network combines the three algorithms' outputs, improving SSIM by over +120%. Hardware profiling confirms 50.4× fewer MACs and a 65 KB INT8 footprint versus a 7.82 M-parameter ResNet-style reference, consuming 0.022% of the Coral Edge TPU's 4 TOPS at 10 fps, enabling real-time VLSI-deployable depth reconstruction.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems, Other Analog/RF Circuits and Systems
Abstract: Metal Oxide Semiconductor Field Effect Transistors are the mainstay for Input/Output and even general analog circuit design in modern integrated circuit technology. The matched wireline driver within the Input/Output domain implements impedance matching to the transmission line. MOSFET-based resistors can be an attractive alternative to varieties of trenched, diffusion and metal resistors, due to being native to a CMOS process, and are small in layout area. This paper presents a theoretical study of a compensation friendly, ON/OFF-controllable candidate to implement resistive matching with minimal pad capacitance using only MOSFETs. Size and cost-constrained biomedical and power-consuming artificial intelligence applications can also benefit from the investigations into MOSFET linearization.

Keywords: Organic and Flexible Circuits and Systems, Emerging Memory and Memristor, Other Beyond CMOS Topics
Abstract: This paper presents an Electronic Design Automation (EDA) flow for modeling resistive random access memories (RRAMs) based on deoxyribonucleic acid (DNA) combined with molecularly engineered quasi-2D organic–inorganic halide perovskite (OHP) hybrid materials. Experimentally benchmarked device models are created in Verilog-A that incorporate various types of variabilities and non-idealities. The model has been successfully integrated into commercially available EDA software, providing a path for integrated CMOS designs. The circuit-level performance is demonstrated in a 1Transistor-1RRAM (1T1R) configuration by integrating read and write circuits in a CMOS process. The variability-aware model enabled the design of a Voltage-Latched Sense Amplifier (VLSA) that senses the read/write states under realistic variability scenarios without failures.

Keywords: Analog Circuits and Systems, Analog, Digital and Mixed Signal Processing
Abstract: Advanced technology nodes such as FinFET and Gate-All-Around (GAA) impose quantized transistor dimensions, eliminating the designer's ability to specify arbitrary channel lengths and widths. Self-cascode stacking with multipliers is widely adopted to restore effective device dimensions and recover the intrinsic gain (g_m*r_o) required for analog design. However, CAD tools treat stacked devices as collections of individual unit transistors rather than a single equivalent device, obscuring small-signal optimization and hindering design intuition. This paper presents a compact analytical model that characterizes an n-device self-cascode stack as a unified equivalent transistor, with closed-form expressions for effective transconductance (g_m,eff), bulk transconductance (g_mbs,eff), transconductance efficiency (g_m/I_D), output impedance (R_out), and effective threshold voltage. The model is validated through SPICE simulations in TSMC 180nm and 16nm FinFET processes, with errors below 3% across all inversion levels and stack configurations, enabling analog designers to treat self-cascode stacks as single-transistor design objects within standard g_m/I_D-based sizing workflows. Finally, the paper draws insights into the effect of stacking on transit time, f_T, and C_gs.

Keywords: Converters, ADC, DAC and others, Analog Circuits and Systems, Physical Design, Test, Verifications
Abstract: Digital to analog converters (DACs) are an integral part of most modern SoCs and are required to be extremely accurate. While a lot of work has been done on reducing the costs involved in accurately capturing its nonlinearity error properties via testing, little work exists on the statistical nature of such properties. This information, if successfully captured, can be used to predict yield without the need for high volume of measurements. This paper analyzes the differential and integral nonlinearity (DNL and INL) properties of unary and binary-weighted DAC structures and shows that the code dependent DNL and INL approximately follow Gaussian distribution. The paper also shows that the extrema (minimum and maximum) of the DNL and INL of the unary weighted and binary weighted DACs respectively follow the Generalized Extreme Value Distribution with very good accuracy. Simulation results using randomly generated unary and binary DACs demonstrate strong agreement between the analytical predictions and the tested DNL/INL statistics.

Keywords: Analog Circuits and Systems, Emerging Memory and Memristor, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Conventional CMOS-based circuits are advancing toward higher reliability, reduced leakage, and robust electrostatic discharge protection. Typical Electrostatic Discharge (ESD) protection structures employ static ballast resistors and diodebased clamps, and struggle to balance low leakage and highspeed performance, while maintaining sufficient transient suppression at nanoscale nodes. We implemented current-controlled memristors as an adaptive current limiting element for ESD protection to enhance the device reliability and energy efficiency in advanced ICs. Using experimental results, a current-controlled model was developed in Verilog-A, and then integrated into an ESD protection circuit under the Human Body Model configuration. The results demonstrated that the memristor effectively limits transient current surges by dynamically adjusting its resistance during ESD events. The findings highlight the potential of current-controlled memristors as scalable, low-power, and self-adaptive elements for next-generation ESD protection in nanoscale CMOS technologies.

Keywords: Emerging Memory and Memristor, In-Memory Computing Circuits and Systems, Image, Video and Multi-Dimensional Signal Processing
Abstract: This paper presents a Cadence-based implementation of an analog edge detector using memristor-crossbar multiply–accumulate (MAC) operations and a 7-nm CMOS interface stage. Two 3×3 crossbar implementations for the gradient kernels (Gx, Gy) as pre-programmed conductance weights, producing small-swing analog outputs that encode horizontal and vertical edge strength. To improve measurability under non-ideal memristor behavior and limited bitline voltage separation, the kernel weights are scaled while preserving relative ratios. A compact 7-nm FinFET-based subtractor and inverter generate an analog edge-indicator output from the Gx/Gy signals. Post-layout/PEX was not performed; results are from transistor-level simulations. With a 0.8 V CMOS supply and a 20 µs stimulus period, the integrated 2‑D Sobel engine produces ~70–110 mV output swing and ~175 µW average power over the steady-state window, while the 7-nm subtractor itself consumes ~160 nW.

Keywords: Emerging Memory and Memristor, Neuromorphic Circuits and Systems, In-Memory Computing Circuits and Systems
Abstract: Time-Domain (TD) computing encodes data in signal transition timings, eliminating power-hungry Analog-to-Digital Converters (ADCs) in Compute-in-Memory (CiM) architectures. However, conventional two-terminal resistive synapses (e.g., Resistive Random-Access Memory) require complex isolation circuitry and suffer from read-disturb. This paper proposes a 3-terminal Ferroelectric Field-Effect Transistor (FeFET) synapse co-designed for TD dendritic circuits. We utilize a Gate-All-Around (GAA) IGZO channel FeFET to decouple the programming and signal paths, simplifying circuit operation and enhancing stability. TCAD simulations demonstrate multi-bit storage by modulating device conductance through the gate terminal, regulating propagation delays in spiking dendritic architectures. The proposed implementation reduces peripheral overhead while enabling spatial-temporal signal processing for edge AI.

Keywords: Emerging Memory and Memristor, Machine Learning at the Edge, Neural Learning Circuits & Systems
Abstract: With the massive impact of AI, energy consumption of required computing resources is trending toward unmanageable. Moving the computation load of these systems from data centers to more novel compute-in-memory hardware would provide vast efficiency gains. Thus, we propose a memristor crossbar circuit for neural network layers, that is reliable, transposable, easily programmable, and extremely energy efficient. We demonstrate the effectiveness of neural networks based on these crossbars first using SPICE at the circuit component level. Then we advance toward larger neural networks, using a simulation approach that can capture circuit level detail (including parasitic resistance, wire resistance, and leakage current) that is able to simulate at speeds orders of magnitude faster than a pure SPICE approach. We then use our simulation tools to discuss the energy requirements of these memristor based neural networks, including tradeoffs between energy, power, area, time, and accuracy. While we demonstrate the effectiveness of this memristor crossbar-based learning system using backpropagation through fully connected layers, this technique can be applied to any algorithm requiring bi-directional vector-matrix multiplication.

Keywords: Regulators, References and Reliability Methods, Other Power Circuits and Systems, Analog Circuits and Systems
Abstract: Modern system-on-chip (SoC) platforms often employ a switching DC-DC converter followed by a low-dropout regulator (LDO) to provide clean local supply voltages for sensitive analog, RF, and mixed-signal circuits. To ensure stable operation under switching noise and dynamic loads, the LDO must deliver high power-supply rejection (PSR) across a wide frequency range while maintaining strong transient performance with a low quiescent current. The proposed LDO employs an RC compensation network that connects an internal high-gain node of the error amplifier (EA) to the LDO output, realizing Miller multiplication to place the dominant pole before the stage driving the pass transistor. This architecture achieves a loop phase margin greater than 60° across the 0–20 mA load range without requiring a large compensation capacitor or an additional gain stage. A 360-pF high-density stacked MOS–MIM–MOM on-chip capacitor enhances high-frequency PSR and transient performance within a compact area. Fabricated in 65-nm CMOS, the fully integrated LDO occupies an active area of 0.12 mm². Measurement results show PSR exceeding 10 dB from DC to 100 MHz, including 28 dB at 10 MHz, with a 5.76-µA quiescent current. Under a 20-mA load step with 100-ns edge time, the regulator exhibits a 38-mV undershoot with a 20-µs settling time and a 25.4-mV overshoot with a 19-µs settling time. The design achieves a 1.31 V·mm² figure-of-merit (FoM), demonstrating an optimal trade-off among PSR, transient performance, quiescent current, and area for low-noise power management in modern SoCs.

Keywords: Regulators, References and Reliability Methods, Other Power Circuits and Systems, Analog Circuits and Systems
Abstract: This paper presents a single-supply, charge-pump-free NMOS capless LDO enabled by a switched-capacitor (SC) gate-refresh technique. Two non-overlapping phase-driven flying capacitors periodically restore the NMOS gate charge, thereby boosting the output transistor gate voltage without a dedicated boosted power supply, while keeping the error amplifier within its nominal low voltage range. An integrated AC-coupled high-pass fast path is used to accelerate large-signal gate modulation during load transients without increasing steady-state switching activity. Designed in 16nm CMOS, transient simulations with a 1pF load capacitor and up to 100mA load current verify correct gate-refresh operation and fast recovery across refresh-timing offsets. A startup-assist device further reduces output establishment time by precharging the gate node and becomes inactive after regulation.

Keywords: Regulators, References and Reliability Methods, Other Power Circuits and Systems, Analog Circuits and Systems
Abstract: This work presents a ring-amplifier LDO using a source-follower first stage and multi-stage replica biasing to achieve supply-noise tracking and suppression. The proposed PVT-resilient bias scheme enables stable operation with only a 10pF output capacitor and low quiescent current. Fabricated in 16nm CMOS, the LDO supports a 0.44-0.9V input range and up to 62mA load current. Measurements show 60dB in-band PSRR, 31dB at 100kHz, and sub-200ns settling for 10mA load steps.

Keywords: Linear and Non-linear Analog Systems, Digital Integrated Circuits, Regulators, References and Reliability Methods
Abstract: This paper presents HCDLDO, a digitally controlled low-dropout regulator that achieves ripple-free regulation and high-resolution current control through a hysteresis-enhanced dual-comparator scheme and a binary-weighted PMOS array. A formal derivation establishes that the no-toggling band depends solely on the resistor ratio and comparator output swing, independent of the reference voltage, and explicit bounds are derived for the trade-off between ripple suppression and transient speed. Validated in a 65nm CMOS process, the regulator operates over a 0.8–1.2V input range with a 30mA maximum load and a 20 μA quiescent current. An 11-bit binary-weighted PMOS array provides 2,048 output levels at 1.4 μV resolution with sub-10 μV ripple, and transient simulations show a 12.1 μs settling time for a 10mA load step. Enabled by the deterministic control-to-current mapping of ripple-free operation, load variations as small as 10 μA are directly reflected in the digital control word without additional sensing circuitry.

Keywords: Regulators, References and Reliability Methods, Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a capacitorless NMOS low-dropout regulator (LDO) for on-chip power management in system-on-chip (SoC) applications. The proposed LDO supports a load-capacitance range of 0–100 pF and a load current range of 100 μA–100 mA, ensuring stable operation for digital loads dominated by parasitic capacitances. A Recycling Adaptive Biasing (RAB) scheme is introduced to adaptively enhance loop dynamics by reusing the existing bias network with minimal overhead. The circuit structure also improves power-supply ripple rejection (PSRR) by reducing intrinsic supply feedthrough while maintaining high loop gain. Implemented in a 55-nm CMOS process, the LDO operates with VIN=1.2 V and VOUT=1.0 V while consuming 38 μA of quiescent current. Simulation results show 0.3 μV/mA load regulation. At a maximum load current of 100 mA, the PSRR reaches −81 dB at 10 kHz and −62 dB at 100 kHz. With a 100-pF load capacitor, the regulator exhibits 48 mV undershoot and 40 mV overshoot for a 100 μA–100 mA load step with a 200 ns edge time.

Keywords: Integrated Biomedical Systems, Biomedical Signal/Image Processing, Wearable Smart Sensor Systems
Abstract: Obstructive sleep apnea (OSA) is a sleep disorder characterized by repeated upper airway obstruction, which, if left undetected, contributes to hypertension, cardiovascular disease, stroke, and cognitive decline. This work presents a real-time, single-lead ECG-based system for automated OSA detection and severity classification. The system is evaluated on the OSASUD dataset, comprising 30 stroke-unit patients with 961,357 annotated seconds of single-lead ECG at 80 Hz, under leave-one-out cross-validation. A comprehensive feature set incorporating heart rate variability (HRV) metrics, nonlinear dynamical features, and morphological statistics is processed by a transformer-based deep learning (DL) model operating on 3-minute ECG windows with a 30-second stride, enabling per-second apnea event detection. The hardware subsystem includes biopotential signal acquisition via surface electrodes, followed by analog amplification, bandpass filtering, and high-resolution analog-to-digital conversion (ADC), with real-time signal processing executed on an embedded single-board computer (SBC). The system achieves 96.7% binary classification accuracy of presence or absence of apnea and 80.0% four-class severity classification accuracy across Normal, Mild, Moderate, and Severe OSA categories via Apnea-Hypopnea Index (AHI) estimation. These results demonstrate that low-cost, single-lead ECG screening can be a clinically viable alternative to traditional overnight sleep studies, with the potential to reduce the cardiovascular and neurological burden of undiagnosed OSA.

Keywords: Sensor Interface Circuits and Microsystems, Image, Video and Multi-Dimensional Signal Processing, Signal Processing Theory and Methods
Abstract: We present the design, implementation, and experimental characterization of a single-pixel free-space frequency-modulated continuous wave LiDAR system with both ranging and imaging capabilities. Prior work has demonstrated that on-pixel interference improves phase stability and reduces noise in short-range FMCW LiDAR. Building on this foundation, we extend the system to enable imaging via beam scanning and depth reconstruction from swept-frequency measurements. We analyze the impact of front-end non-idealities, including beat-frequency SNR, laser linewidth, and phase noise, on system performance, and evaluate computational reconstruction methods for improving image quality. These results provide a pathway toward scalable multi-pixel FMCW LiDAR imaging systems.

Keywords: Streaming and Human-Computer Interactions, Hardware-Software Co-Design, Technologies for Smart Sensors
Abstract: Current assistive technologies for blind and visually impaired users present web content in a linear, one-dimensional format, limiting spatial understanding and navigation efficiency. This work introduces the Tactile Web Browser, a modular two-dimensional tactile interface that converts webpage layouts into physical representations using raised keycaps actuated by bistable solenoids. HTML elements are encoded through distinct configurations of raised keycaps, enabling rapid recognition through touch. A dual-mode interaction model allows users to explore content via short presses, which trigger audio playback of the associated element, and to activate elements via sustained presses. The system integrates scalable hardware modules, distributed control electronics, and a real-time DOM parsing pipeline. A prototype demonstrates feasibility at a cost of approximately 400, significantly lower than existing multi-line tactile displays.

Keywords: Analog Circuits and Systems, Physical Design, Test, Verifications, Other AI and Edge Topics
Abstract: This work presents AnalogMind, a tool-augmented pipeline for analog circuit design, optimization, and education. The system accepts design specifications through natural language or configuration files, compiles them into parameterized SPICE netlists, and evaluates designs using closed-form equations, CMA- ES optimization, Pareto NSGA-II multi-objective search, and Monte Carlo yield analysis. A hardware prototype validates simulation results against a physically tunable Sallen-Key low-pass filter controlled by an STM32 microcontroller. Benchmarked against GPT-4o, GPT-4o- mini, and Claude Sonnet 4.6 on 87 circuit design tasks, AnalogMind achieved an 80.5% pass rate compared to a next-best of 36.8%, demonstrating that a simulation-backed pipeline significantly outperforms general-purpose LLMs on analog circuit design tasks.

Keywords: Human/brain-Machine Interfaces, Wearable Smart Sensor Systems, Machine Learning at the Edge
Abstract: Brain-computer interfaces (BCI) based on motor imagery require lengthy calibration and high-density electrode arrays, limiting practical deployment. This paper presents a calibration-free motor imagery classification system using a 4-channel electroencephalogram (EEG) configuration on consumer-grade hardware. We introduce MSAENet4Ch, a multi-scale temporal attention network with domain-adversarial training designed for low-channel-count EEG. The model uses parallel temporal convolutions, squeeze-and-excitation attention, temporal attention pooling, and gradient reversal for subject-invariant feature learning. Evaluated on the PhysioNet Motor Imagery dataset (109 subjects, subject-level split), the system achieves 43.22% four-class accuracy (chance = 25%) on 16 unseen subjects with zero task-specific calibration. Comparison with a vanilla EEGNet baseline shows a 4.56 percentage-point gain in test accuracy. Post-hoc temporal aggregation using majority voting and probability accumulation was also evaluated, but it reduced performance relative to the single-epoch baseline. When deployed on an NVIDIA Jetson Orin Nano, inference is completed in 0.75 ms, demonstrating real-time feasibility for edge-based BCI applications.

Keywords: Sensor Interface Circuits and Microsystems, Other Power Circuits and Systems, Analog Circuits and Systems
Abstract: Single-photon counting modules (SPCMs), fundamental to LiDAR systems operating across a wide dynamic range, rely on high-speed active quenching circuits (AQCs) to maximize throughput under elevated photon arrival rates. Recent advancements in AQCs have been focused on increasing the maximum photon count-rate while ensuring no degradation in critical detector performance metrics, including the photon detection efficiency (PDE) and afterpulse probability (APP). While the relationship between key detector performance metrics, such as PDE, dark current, avalanche gain, response time, and temperature is well understood, thermal effects on the AQC with respect to the maximum achievable count-rate has not yet been explored. A key tradeoff between maximum count-rate and PDE across excess bias is explored in detail, and a system level optimization strategy is provided that maximizes both performance metrics allowing the single-photon counting module to operate at high sensitivity at the maximum photon arrival rate.

Keywords: Machine Learning and Cognitive Radio, 5G & 6G Circuits and Systems, RF Front-End Circuits
Abstract: This paper presents a multi agent neurosymbolic artificial intelligence architecture to dynamically adapt operating parameters of radio frequency (RF) transceivers. The proposed dual branch architecture combines deep learning feature extraction with deterministic symbolic reasoning, leveraging sensed physical parameters such as signal power and spectrum occupancy, to ensure self-adapting and robust hardware safety. Component specific control agents are trained using digital twins and integrated with physical hardware via shared memory space and socket-based inter-process communication for low latency. Experimental results demonstrate accurate modeling and rapid parameter adaptation for error vector magnitude optimization, providing a scalable foundation for intelligent self-adapting RF transceivers.

Keywords: Other AI and Edge Topics, Hardware-Software Co-Design
Abstract: Individuals with diabetes require continuous blood glucose monitoring, but current methods such as finger-prick glucometers and embedded lancets are painful, expensive, and invasive. WISE-E is a wearable edge-AI smartwatch that uses fingertip photoplethysmography (PPG) to assess blood glucose in real-time. PPG-derived signal characteristics and user demographic data are fed into a Multi-Layer Perceptron (MLP) model trained for blood glucose regression. The MLP had a mean absolute percentage error (MAPE) of 16.67%, with 67.49% of estimates clinically accurate (Clarke Error Grid Analysis Zone A) and 31.30% clinically acceptable (Zone B). The trained model was quantized to a TFLite C-header format and deployed on an ESP32-based wear-able edge device equipped with an interactive GUI, allowing for on-device real-time inference. The deployed model maintained a MAPE of 20.86%, with over 98% of predictions falling within CEGA Zones A and B, suggesting that PPG-based Edge-AI is a feasible scheme for non-invasive blood glucose awareness, though further validation is required before clinical deployment.

Keywords: Signal Processing Theory and Methods
Abstract: This paper explores the application of compressive sensing to a single-pixel FMCW LiDAR testbench. The goal is to reduce acquisition time while maintaining acceptable spatial resolution by replacing raster scanning with compressed measurement strategies.

Keywords: Sensor Interface Circuits and Microsystems, Analog, Digital and Mixed Signal Processing, Other Signal and Image Processing
Abstract: This work presents a hardware-in-the-loop FMCW LiDAR test platform for evaluating tunable lasers and photodetectors under realistic operating conditions. The platform combines real-time FPGA-based signal processing with dedicated optical device characterization, enabling beat-frequency extraction, FFT-based spectral analysis, and distance measurement directly from the photodetector output. Laser evaluation is performed through delay self-heterodyne interferometry to extract linewidth and phase noise, while detector evaluation quantifies responsivity and effective noise performance within the LiDAR receive chain. By unifying embedded ranging analysis with source and detector characterization, the platform provides a practical framework for validating fabricated photonic devices for LiDAR applications.

Keywords: Wireless Mobile Circuits and Systems and Connectivity, Hardware Security, Other Analog/RF Circuits and Systems
Abstract: Language barriers and auditory limitations often hinder accessibility in public and educational spaces. This paper presents the design and implementation of an affordable audio transmission and translation system prototype. Using two single-board computers (SBCs) and specialized transceiver boards, the system operates on the 902–928 MHz Industrial, Scientific, and Medical (ISM) band. The receiver supports dual-mode functionality: a real-time raw audio stream for hearing assistance and a low-latency translation stream for multilingual support. Translation is handled via the Google Cloud Text-to-Speech (TTS) API. To ensure privacy and data integrity, the network employs end-to-end AES-128 encryption.