Keywords: Other Beyond CMOS Topics, AI Digital Hardware, Accelerators, and Circuits, Other AI and Edge Topics
Abstract: In this paper, we report a novel memory device technology that combines non-volatility in gain cell (GC) DRAMs. The device can be operated as high-density nonvolatile Memory (NVM) or GC DRAM. The hybrid operation is demonstrated using TCAD and Cadence simulations. Finally, application of these hybrid memories is established in low-power edge AI architectures, particularly for intermittently powered systems using harvested energy requiring frequent back-ups.

Keywords: Emerging Memory and Memristor, In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: Artificial intelligence (AI) based applications are becoming increasingly integrated into everyday life; however, the computational cost of executing AI training is becoming a challenge, mostly due to the delay and power consumption from large data movement from memory devices. Resistive Random Access Memory (RRAM) has shown promising results by enabling in-memory computing, hence alleviating the data-movement bottleneck. This paper presents a detailed design for the RRAM unit cell as well as RRAM array peripheral circuit architecture for memory computation using a silicon-proven 4Kb (64 × 64) 1T1R RRAM array in a 65 nm CMOS technology node. This work paves the path for design and hardware implementation of custom RRAM-based AI accelerators.

Keywords: Emerging Memory and Memristor, Neuromorphic Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: One of the obstacles limiting the fabrication, modeling, and large-scale adoption of memristors is its relatively large variability in electrical characteristics. To address this challenge, we utilize a kinetic Monte Carlo (KMC) simulation tool to illustrate and quantify structural design changes that can lead to a significant reduction of electrical variations in metal-oxide (MOx) thin-film memristors, while also enhancing their switching performance. In particular, we explore various MOx interface layer options through which oxide diffusion occurs, and where subsequent filamentation for state change typically starts. Both chemical (MOx interface layer type) and physical (thickness and shape) properties of interface layers are investigated via KMC simulations. It is found that a 2 nm TaO2 interface layers in HfO2-based memristors offer the best improvement in simple layer architecture. Inclusion of a cubic or conical seed layer in the interface layer reduces Ron and Roff resistance variations from 6% to 3% range in the KMC simulations. The electrical properties of the proposed devices are then captured into the compact (SPICE and Verilog-A) models to extract circuit performance in crossbar devices, essential for neuromorphic applications and AI/ML accelerators. Their performance is assessed as a function of crossbar size and parasitics, showing that delay, power, and multiply-and-accumulate errors remain well below 8% for 𝑛 = 16.

Keywords: Emerging Memory and Memristor, In-Memory Computing Circuits and Systems, Other Beyond CMOS Topics
Abstract: TaOx-based resistive random access memory (RRAM) shows promise as a technology for next-generation non- volatile memory applications due to its simple structure and scalability. Resistive switching in these devices arises from the formation and rupture of conductive filaments within the TaOx layer driven by oxygen ion migration. Although the switching mechanism is generally stable, device performance often suffers from variability and limited reliability. In this work, we investi- gate the impact of different oxygen exchange layer (OEL) met- als on the switching characteristics of Pt/TaOx/OEL/Pt RRAM devices. Four OEL materials (Ti, Al, Ta, and Pt), spanning a range of oxygen vacancy defect formation energies, are integrated on a single wafer to enable direct comparison under identical fabrication conditions. Device performance is evaluated by statistical analysis of the forming voltage, memory window (Roff /Ron), and representative current–voltage (I–V ) characteristics across multiple DC switching cycles. The correlation between defect formation energy and switching behavior is not monotonic across the full material series: while Pt exhibits the largest median memory window, it also shows the poorest switching consistency, whereas Ta achieves the highest cycle yield and most stable switching. This indicates that memory window, variability, and cycling reliability are governed by compounding defect dynamics rather than defect formation energy alone. These findings provide insight into the role of OEL selection in optimizing TaOx-based RRAM performance.

Keywords: In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, AI Digital Hardware, Accelerators, and Circuits
Abstract: This paper presents a charge-domain analog compute-in-memory (CIM) macro that integrates accumulation and analog-to-digital conversion (ADC) using an unified capacitor architecture. By re-utilizing the same binary-weighted capacitor array for both multiply-and-accumulate (MAC) operations and successive approximation register (SAR) ADC, the design achieves high integration density and energy efficiency. The proposed macro is based on 9T1C SRAM bitcell and provides 4-bit precision for both inputs and weights. MAC operations are performed via conditional capacitor switching. This creates an analog voltage on a shared top plate, which is then digitized using a 5-bit SAR ADC. This capacitor reuse eliminates unnecessary capacitive digital-to-analog converter (CDAC) structures in the SAR ADC, reducing area and switching power while improving matching. Pre-layout simulations in a 65-nm CMOS technology node show a peak throughput of 2048 GOPS and an energy efficiency of 438 TOPS/W at a 1.2 V supply, while achieving 94.2% accuracy on the MNIST dataset. This architecture enables scalable, low-power, high-throughput edge AI inference.

Keywords: RF Front-End Circuits, Other Analog/RF Circuits and Systems, Wireless Mobile Circuits and Systems and Connectivity
Abstract: An ultra-low-power wake-up receiver for wireless sensor network applications is presented. The novel receiver architecture features on-chip double-sideband generation and phase noise cancellation. The RF front-end multiplies an incoming RF signal with a low-frequency, low-noise oscillator to generate a double-sideband signal on-chip. This signal is then down-converted using a low-power RF local oscillator with relaxed phase noise requirements. A subsequent squaring stage cancels the phase noise introduced by the LO and recovers a baseband signal. By generating the double-sideband signal on-chip, the proposed receiver combines the power advantages of two-tone receivers with the spectral efficiency of single-carrier signaling. The 2.4 GHz receiver RF front-end is fabricated in 22nm FinFET, consuming a total power of 51.5 µW and achieving a noise figure of 18.1 dB.

Keywords: RF Front-End Circuits, Quantum Hardware Systems, Quantum Architecture and Design
Abstract: This paper presents a wideband cryogenic low-noise amplifier (cryo-LNA) designed in a 130 nm SiGe BiCMOS process, specifically optimized for the high-speed readout of superconducting nanowire single-photon detectors (SNSPDs). To capture the sub-nanosecond pulses generated by SNSPDs, the cryo-LNA incorporates a two-stage common-emitter topology with resistive-capacitive shunt feedback and inductive peaking techniques. Meanwhile, the optimization of circuit performance is optimized by the cryogenic process design kit (PDK) based on measured SiGe HBT data. The fabricated cryo-LNA achieves a stable gain of 20~23 dB across 0.1 MHz~2.5 GHz, with the noise-temperature of 1.54~6 K. Integrated with SNSPD, the readout system demonstrates the amplification of 0.5 mV input pulse to 7.2 mV while consuming only 1.08 mW and a compact chip area of 0.304 mm², providing a scalable front-end solution for large-scale multi-pixel SNSPD arrays.

Keywords: Other Analog/RF Circuits and Systems, Other Wireless and Communications Topics
Abstract: A wideband input-matched common-gate (CG) continuous-time linear equalizer (CTLE) is implemented in 28-nm CMOS technology, incorporating an active inductor load to enhance high-frequency response. The proposed architecture achieves wideband input matching to minimize signal reflections and ensure signal integrity, while delivering power-efficient equalization with a horizontal eye opening of 45.25 ps and a vertical differential eye opening of 687.37 mV. The design ensures reliable operation for channels with up to 9 dB loss, while consuming only 5.37 mW from a 0.9 V supply. The resulting figure of merit (FOM) of 0.037 pJ/bit/dB demonstrates an energy-efficient and compact solution for next-generation high-speed SerDes applications.

Keywords: Quantum Hardware Systems, Electronic/Photonic Integration, Analog Circuits and Systems
Abstract: This paper presents a compact, inductorless shunt-feedback transimpedance amplifier (SF-TIA) designed in a 130nm SiGe BiCMOS process for quantum-limited optical receivers. To accommodate the massive photodiode capacitance required for high quantum efficiency, the design overcomes the fundamental noise-bandwidth trade-offs of single-stage architectures. The proposed TIA utilizes a multi-gain stage incorporating a Cherry-Hooper topology. This configuration leverages inter-stage impedance mismatching to push the internal pole to high frequencies, significantly enhancing the overall gain-bandwidth product. Comprising the core TIA and an output buffer, the integrated circuit achieves a 10GHz closed-loop bandwidth and a transimpedance gain of 60dBΩ when loaded with a 350fF input capacitance. The receiver achieves an equivalent input-referred noise density of 5.2 pA/√Hz over a 8.4GHz bandwidth while consuming a total of 73.4mW of power.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This note presents techniques for converting a two-dimensional, bivariate, single-input single-output (SISO) linear time-varying system (LTVS) representation into a one-dimensional, single-variable representation. The key results exploit the structure of the two-dimensional Laplace transform (2DLT) to characterize system behavior.

Keywords: Digital Filters, Other Digital Circuits and Systems, Analog Circuits and Systems
Abstract: This paper presents a novel design framework for high-accuracy digital differentiators based on a new biquadratic structure in the continuous-time domain and its discrete-time realization via the bilinear transformation. The continuous-time model is obtained from a simple fractional-order formulation and provides a very good approximation to the ideal differentiator, with linear phase and almost ideal magnitude of frequency responses over several decades of frequency. The discrete-time implementation preserves these characteristics within the useful band while requiring only a second-order IIR structure, which leads to reduced computational complexity. MATLAB simula- tions are used to illustrate the performance of the proposed differentiator and to compare it with conventional designs.

Keywords: Digital Integrated Circuits, Processor and Memory Design and Architectures, Other Digital Circuits and Systems
Abstract: This paper presents a rail-to-rail D-latch based on a cross-coupled PMOS load to improve switching performance. In conventional rail-to-rail D-latch structures, contention occurs between the pull-up and pull-down paths during input transitions due to the feedback of the previous output to the PMOS gate. In the proposed design, the PMOS load is controllably turned off during the transition, allowing the NMOS network to initiate the decision-making process, which is later reinforced by the PMOS feedback. This approach significantly reduces contention and enhances switching speed. The latch is implemented in 180 nm CMOS technology and evaluated using Cadence Virtuoso. Simulation results demonstrate improved performance, achieving D to Q and clk to Q delays of 282.5 ps and 289.2 ps, respectively, along with a low power-delay product (PDP) of 15.02 fJ.

Keywords: Neuromorphic Circuits and Systems, Analog Circuits and Systems, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Memristive synapses are attractive candidates for spiking neuromorphic hardware; however, most existing STDP circuits rely on plasticity mechanisms that implicitly assume symmetric potentiation and depression updates. In filamentary memristive devices, the SET and RESET processes often exhibit strongly asymmetric kinetics, where the RESET operation can be orders of magnitude faster than the SET operation, imposing practical constraints on implementing biologically plausible plasticity in hardware. In this work, a device-aware memristive reconfigurable STDP circuit is proposed that explicitly accounts for the asymmetric SET/RESET dynamics of filamentary devices enabling adjustable conductance-update resolution. By shaping the effective width of the transistors within the STDP circuit, the long term potentiation (LTP)/long term depression (LTD) rate can be tuned, allowing heterogeneous plasticity across synapses in the network, which is consistent with biological observations. A key feature of the proposed architecture is synapse-specific reprogrammability: per-synapse RESET modulation enables different STDP learning rates across the network without modifying spike-timing rules. The resulting architecture provides a practical pathway toward reconfigurable, device-aware STDP implementations that align learning dynamics with the physical constraints of memristive devices.

Keywords: Neuromorphic Circuits and Systems, Neuromorphic System Algorithms and Applications, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits
Abstract: Spiking neural network simulators such as NEST and Brian2 provide no mechanism to enforce fabrication-compatible parameters or export transistor-level netlists, causing parameter mismatches when designs reach analog neuromorphic chips. We present NeuroMatrix, a hardware-realistic neuromorphic simulation framework that constrains all parameters to analog-implementable ranges from inception and provides a direct path to foundry verification via Fabrica's Circuit IR. The architecture employs distributed columnar encoding with Indiveri's subthreshold LIF neurons (Cmem = 10 pF, τm = 20 ms), built on an associative memory region (7,500 neurons, 525K synapses) within a 25,100-neuron hierarchical architecture. Validation demonstrates 993 semantically encoded concepts at 83.1% ± 3.7% distinctiveness, approaching the classical 0.138N Hopfield reference with no capacity-dependent degradation. Multi-sample cue-informed pattern completion (not uncued free recall) achieves 80% accuracy at full scale. Mean instantaneous sparsity (0.71%) constrains dynamic per-neuron power to the microwatt range consistent with fabricated analog chips (bias-generation and AER routing power excluded, deferred to tape-out). Three-level verification spanning behavioral, transistor-level (EKV 2.6), and foundry-accurate (IHP PSP103) simulation confirms circuit feasibility before fabrication.

Keywords: Digital Integrated Circuits, Neuromorphic Circuits and Systems, AI Digital Hardware, Accelerators, and Circuits
Abstract: Spiking neural networks (SNNs) promise energy-efficient temporal processing, but the choice of neuron model affects both task accuracy and hardware cost. We compare three mechanisms for enriching temporal processing in SNNs---heterogeneity, adaptation, and synaptic delays---on auditory benchmarks (SHD, SSC) under controlled conditions, analyzing per-neuron arithmetic cost, state storage, and total energy. Our key finding is that constrained adaptive LIF (cAdLIF) neurons in a feedforward topology outperform recurrent heterogeneous LIF networks while eliminating recurrent connections, the dominant contributor to synaptic energy. Parameter-efficiency sweeps show that cAdLIF networks with 4x fewer parameters exceed the LIF accuracy ceiling at any size, producing 30% fewer total spikes at matched accuracy. Post-training quantization confirms that 10-bit fixed-point incurs <1% accuracy loss on both benchmarks, and RTL synthesis (Yosys + SKY130) shows that, at matched 256 x 2 size, feedforward cAdLIF is 2.4x smaller in silicon area than recurrent LIF, despite its higher per-neuron cost.

Keywords: Neuromorphic System Algorithms and Applications, Neural Learning Circuits & Systems, Machine Learning at the Edge
Abstract: This work presents a lightweight sparsity-regularized spiking neural network (SR-SNN) for electroencephalography (EEG)-based affective computing on edge AI systems. An adaptive delta modulation (ADM)-based encoding is employed to generate sparse spike representations via channel-wise threshold adaptation. A compact SNN with leaky integrate-and-fire (LIF) neurons performs efficient spatio-temporal feature extraction, while sparsity regularization reduces spike activity and synaptic operations for improved computational efficiency. The proposed design targets hardware-efficient inference with low memory utilization, low latency, and high throughput. Experimental evaluation on the DEAP dataset demonstrates competitive classification accuracy with significantly lower spike rates. Deployment on NVIDIA Jetson Orin Nano and Qualcomm AI Hub Workbench validates low-latency, high-throughput performance across embedded GPU and mobile NPU platforms, demonstrating suitability for real-time neuromorphic edge computing applications.

Keywords: Neural Learning System Algorithms and Applications, Neuromorphic System Algorithms and Applications
Abstract: Reservoir computing (RC) provides a computationally efficient approach for performing computational tasks on temporal dynamic signals. However, the effectiveness of an RC system depends substantially on the dynamical behavior of the reservoir. The requirements and limitations of reservoirs in RC systems are explored, with particular focus on the conditions under which a reservoir satisfies the echo state property (ESP), the fading memory property (FMP), or both. The ESP ensures that reservoir states become asymptotically independent of initial conditions, whereas the FMP describes the diminishing influence of past inputs on present states. The effects of these properties on memory retention and response to input dynamics are analyzed, along with their implications for prediction, classification, and overall system reliability. A clearer understanding of the roles of the ESP and FMP in RC performance is thereby established, providing guidance for the design and evaluation of robust RC architectures, particularly those intended for the analysis of biomedical datasets.

Keywords: Digital Filters
Abstract: A widely used method for reducing word-length in Cascaded Integrator Comb (CIC) filters is shown to be suboptimal when quantization noise is measured over a limited bandwidth. Using a frequency domain view enables word length truncations to be made to meet noise specifications over a defined bandwidth. This significantly reduces in-band quantization noise, enabling the output word-length to be reduced, with additional hardware savings in the next stage of filtering. Another application is reducing the word-length of over sampled data without decimation and without an error feedback loop.

Keywords: Converters, ADC, DAC and others, VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Mixed-Signal RF and Baseline Circuits
Abstract: Achieving linearity and wide delay programmability in digital-to-time converters (DTC) is limited by slope distortion and charge sharing errors. This work introduces a constant slope delay generation method using a three-capacitor redistribution structure for coarse range extension and fine resolution adjustment while preserving a fixed discharge slope. The prototype in TSMC 180 nm CMOS delivers 488 fs resolution, 13-bit control, INL of 1.5 LSB over 4 ns delay, and 0.5 mW at 25 MHz. This high-resolution standalone DTC architecture establishes the foundational core for future chip-level integration, making it ideally suited for reference-edge alignment in low-jitter fractional-N all-digital PLLs.

Keywords: Converters, ADC, DAC and others
Abstract: Error-feedback noise-shaping (EF NS) SAR ADC nowadays is a popular alternative to discrete-time (DT) delta-sigma ADCs due to their simplicity and efficiency. In this paper, we propose a 2nd-order EF NS SAR, implemented with a passive, cap-stacking FIR filter alongside a ring amplifier that operates as a residue amplifier. To avoid the charge stored in FIR and the capacitive DAC (CDAC) from being used up, the ring-amplifier-based residue amplifier was modified into a differential-difference structure, so that it does not take the charge from the preceding stage by sampling its input. Designed in 0.18µm CMOS technology, the EF NS SAR ADC achieves 84.9 dB SNDR in 20-kHz bandwidth, operating under 1.2 V supply and 10.24 MS/s sampling rate, while consuming 521.5 µW of power.

Keywords: Converters, ADC, DAC and others, VCO’s and Frequency Multipliers, PLL’s and Synthesizers, Mixed-Signal RF and Baseline Circuits
Abstract: A memory-assisted noise-shaping time-to-digital converter (TDC) based on a dynamic-threshold noise-shaping bang–bang phase detector (S-BBPD) is presented. Embedding a state-dependent decision threshold within a delay-based onebit quantizer achieves intrinsic first-order noise shaping while suppressing stochastic toggling near zero timing error. A unified analytical model based on Bussgang linearization derives closedform expressions for detector gain, internal state variance, and signal- and noise-transfer functions. This analysis reveals a unique optimum memory coefficient α⋆ that minimizes inputreferred quantization noise. An energy-based adaptation law autonomously tracks α⋆ under process, voltage, and temperature (PVT) variation using only local statistics of the binary output sequence, with convergence guaranteed by strict convexity of the quantization-noise surface. Behavioral simulations confirm robust, self-regulated noise-shaping recovery across PVT excursions, demonstrating a fully digital, calibration-light solution for wideband ADPLL applications.

Keywords: Image, Video and Multi-Dimensional Signal Processing, Signal Processing Theory and Methods, Other Signal and Image Processing
Abstract: This paper presents a robust method for gravel road surface segmentation, focusing on rural, unmarked environments where hard shadows and texture variations pose significant challenges. Traditional segmentation methods often fail to distinguish between road surfaces and surrounding vegetation due to the impact of shadows and inconsistent textures. To address this, the proposed method combines chromatic clustering in the CIELAB color space with Gabor-based texture analysis applied to the luminance channel L^* after multi-scale Retinex processing for shadow mitigation. The monocular-camera image processing pipeline is designed to identify and isolate gravel road surfaces from grass, brush, and tree-lined shoulders, ensuring accuracy even in shadowed regions. This work provides a practical foundation for future neural network-based approaches by offering an effective segmentation method that can generate labeled image sets for training. Experimental results demonstrate the effectiveness of the approach in real-world rural scenarios, suggesting a promising path toward driver assistance systems for challenging, unmarked terrains.

Keywords: Image, Video and Multi-Dimensional Signal Processing, AI-IoT Systems and Applications, Other Signal and Image Processing
Abstract: Infinite‑ISP is an emerging open‑source image signal processing (ISP) framework, but its full 21‑block pipeline is too computationally intensive for real‑time or embedded platforms. This work presents a compact, hardware‑friendly reduced ISP pipeline derived from module‑level profiling across multiple RAW datasets. The proposed design removes costly iterative stages while preserving essential radiometric and color‑processing functions, resulting in approximately 80% lower processing time compared to the full Infinite‑ISP pipeline. To support next‑generation polarization‑sensitive sensors, we also integrate a lightweight monochrome polarization demosaicing module based on Edge‑Aware Residual Interpolation (EARI), enabling efficient MPFA/CPFA reconstruction. Experiments on low‑light and polarization datasets show improved PSNR/FSIM fidelity relative to the full pipeline. Synthesized in a 28 nm CMOS process at 200 MHz, the reduced ISP achieves 200 MP/s throughput with 0.67 mm² area and 21.486 mW power, demonstrating suitability for real‑time, low‑power embedded imaging systems.

Keywords: Machine Learning at the Edge, Analog, Digital and Mixed Signal Processing, Technologies for Smart Sensors
Abstract: As edge computing proliferates, enabling real-time speaker verification on resource-constrained devices has become critical to privacy and efficiency. However, the field's trajectory toward massive deep learning (DL) embeddings (e.g., x-vectors, ECAPA-TDNN) introduces severe memory and latency overhead, rendering them nonviable for ultra-low-power micro controllers. To address this, we present a comprehensive profiling framework that systematically evaluates 225 feature-classifier permutations, comparing traditional digital signal processing (DSP) features against modern DL embeddings under strict edge constraints. Experimental profiling demonstrates that, while DL embeddings dominate raw accuracy, traditional DSP representations coupled with lightweight classical classifiers can provide the optimal design choice for the extreme edge. Specifically, an RBF-kernel support vector machine (SVM) trained on functionally pooled MFCC and zero-crossing rate (ZCR) / RMS energy features achieves one of the definitive Pareto-optimal configurations for deployment on 512 KB memory architectures.

Keywords: Machine Learning at the Edge, AI-IoT Systems and Applications, Image, Video and Multi-Dimensional Signal Processing
Abstract: Non-Maximum Suppression (NMS) is a key bottleneck in object detection, with O(N²) complexity and heavy reliance on floating-point arithmetic. We propose Bit-Parallel Non-Maximum Suppression (BP-NMS), a new approach that evaluates spatial overlap using fast bitwise primitives. By quantizing bounding boxes into grid-aligned bit-vectors, BP-NMS replaces expensive floating-point Intersection-over-Union (IoU) checks with single-cycle bitwise AND and population count instructions. We also introduce a Global-Canvas variant that achieves O(N) complexity by performing single-pass suppression against an accumulated spatial bitmask. On COCO, BP-NMS achieves high area coverage retention (96.9%) compared with standard NMS at high grid resolutions. BP-NMS Global exhibits strict linear scaling; as N increases from 1,000 to 20,000, latency grows from just 1.1 ms to 12.7 ms, accelerating standard baselines by 17× to over 137× at the extremes. BP-NMS is a scalable, hardware-portable solution for platforms with efficient bitwise and population-count support, suitable for both edge devices and inference servers.

Keywords: Hardware-Software Co-Design, Machine Learning at the Edge, Biomedical Signal/Image Processing
Abstract: This paper presents the deployment of a speech-based Alzheimer’s disease classification CNN on the Xilinx Kria KV260 edge FPGA platform using hardware–software co-design. A lightweight 76,082-parameter network operating on log-Mel spectrograms is trained on a combined 160-sample dataset and quantized to INT8 using post-training quantization with the Vitis-AI toolchain. Audio preprocessing runs on the ARM Cortex-A53, while inference is offloaded to the DPUCZDX8G Deep Processing Unit. The FP32 baseline achieves 87.5% accuracy; post-training INT8 quantization yields 84.4% for both CPU and FPGA configurations, with INT8 FPGA and INT8 CPU producing identical predictions under strict preprocessing alignment. The deployed system achieves 0.876 ms inference latency and 1140+ FPS throughput, a 7.4× speedup over FP32 CPU execution at 157.7 FPS/W energy efficiency, compared to 26.2 FPS/W for CPU inference. These results confirm reliable FPGA acceleration for biomedical speech inference and highlight the critical role of preprocessing alignment and quantization consistency in edge deployment.

Keywords: Hardware Security, AI Digital Hardware, Accelerators, and Circuits, Hardware-Software Co-Design
Abstract: Machine learning (ML) accelerators are widely deployed in edge and embedded systems, making their reliability and security increasingly crucial. Soft errors and intentional bit level disturbances can impair the multiply–accumulate (MAC) processes that control ML workloads, where even a single bit fault in the accumulator may significantly affect inference results. While many previous solutions rely on system-level security or high-overhead detection frameworks, lightweight MAC level fault detection methodologies remain limited. This work presents a MAC-level fault detection and classification architecture based on dual modular redundancy (DMR) combined with a lightweight decision-tree-based TinyML classifier. The design employs parallel golden and fault-injected MAC units with real-time output comparison for fault detection, while a decision tree-based TinyML model utilizes runtime signals to classify fault types. The proposed architecture is implemented on a Xilinx Artix-7 (Nexys A7) FPGA operating at 100 MHz. Experimental results demonstrate near-complete fault detection coverage (98–100%) across all 32 accumulator bits, with constant one-cycle detection latency and minimal hardware overhead, without requiring additional DSP or BRAM resources.

Keywords: Other AI and Edge Topics, Machine Learning at the Edge, Other Neural and Neuromorphic Circuits and Systems Topics
Abstract: Continual learning (CL) enables artificial intelligence (AI) systems to adapt to new information while mitigating catastrophic forgetting (the loss of previously acquired knowledge). The popularity of these algorithms in safety critical domains has necessitated interpretability methods to understand model predictions. One such method derived from Shapley Additive Explanations (SHAP) is SHAP Consistency (SHAPC). Its global variant, SHAPC-Mean, quantifies the decision attribution stability throughout the learning process. The existing SHAPC-Mean requires iterations over all samples and task-pair combinations, making it computationally expensive. We propose three optimized approaches to computing SHAPC-Mean that reduce samples, task-pair iterations, or a combination of both. This decreases overall computation time while maintaining metric performance. Additionally, we introduce a classwise SHAPC-Mean metric to assess potential class-dependent biases. We demonstrate that the SHAPC-Mean is class-independent.

Keywords: Artificial Intelligence for Complex Networks and Nonlinear Systems, Converters, ADC, DAC and others, Hardware-Software Co-Design
Abstract: Designing high step-down, high-current power converters traditionally relies on time-consuming manual topology iteration and trial-and-error parameter tuning. This paper proposes an automated framework combining Large Language Model (LLM)-driven circuit topology evolution with Multi-Objective Bayesian Optimization (MOBO). Candidate topologies are represented in Verilog-AMS while a Topology-Performance Table (TPT) leverages simulation-derived parameter sensitivities to provide structured feedback for iterative LLM refinement. Results show that while MOBO optimizes parameter tradeoffs within restricted search spaces, topology evolution successfully explores alternative structural directions, yielding a well-balanced and practically superior design.

Keywords: Analog Circuits and Systems, Linear and Non-linear Analog Systems
Abstract: This paper presents a sizing workflow for translinear circuits implemented with weakly-inverted CMOS devices that ensures accurate calculation over the full input range. Unlike traditional automated sizing frameworks where design targets a nominal bias, the proposed approach performs optimization over a wide operating range. In the proposed framework, feasibility is assessed via neural-network surrogate models trained on targeted simulations of drain-to-source voltages, bandwidth, and statistical variability. These surrogates capture the circuit's behavior across critical operating points and are utilized within a multi-objective genetic search to identify optimal designs. Verified on a translinear multiply/divide circuit in TSMC 65nm CMOS technology, schematic simulations of the candidate designs obtained via the proposed framework achieve a mean absolute percentage error (MAPE) between 3.62% and 3.79% across a four-decade input current range (10 pA to 100 nA). Simulated bandwidths range from 211 Hz at 10 pA to 15.79 kHz at 10 nA. These results show that incorporating domain-wide feasibility in device sizing can achieve high-precision in analog computing circuits typically operating over wide input ranges.

Keywords: Other Power Circuits and Systems, Power Management of Electric Vehicles
Abstract: This paper presents a unified analytical framework for comparing three inverter topologies for medium-power motor drives: a conventional two-level SiC MOSFET inverter, a three-level neutral-point-clamped silicon IGBT inverter (NPC), and a three-level T-type (T-NPC) silicon IGBT inverter. The device models were parameterized using the manufacturer’s datasheet characteristics and validated through detailed PLECS simulation models for railway traction drive systems. PLECS-based validation is commonly employed during the design and optimization stages of industrial power electronic systems prior to the prototype development and hardware testing. The framework combines electrothermal device models, topology dependent loss equations, an equivalent RLC motor model, and standardized thermal networks with equal output power. A 33 kW PMSM drive supplied from a 2500 V DC bus is analyzed using PLECS simulations at 5, 10, 20 and 40 kHz switching frequencies to assess electrical and thermal performance. Both analytical results and simulations clearly demonstrate that the SiC MOSFET offers an inherent advantage for medium- to very high power applications, especially where superior thermal performance in a compact form factor is critical.

Keywords: Other Power Circuits and Systems, Power Management of Electric Vehicles
Abstract: In this paper, we present simulation results of 1500V-1900V class 4H-SiC implantation and epitaxial MOSFET (IEMOSFET) structures. These structures are attractive due to the low doped epitaxial p-type layer which improves the channel mobility in the on-state, along with a high doped implanted layer to prevent punch-through and to give excellent off-state characteristics. In this work, a comparison of the IEMOSFETs with and without buried channel layers has been performed to obtain a trade-off between process complexity and device performance. Since interface traps can affect both device characteristics and long-term reliability, we performed a comparative study of the high trap density vs reduced trap density cases, where the low trap densities can be obtained using recently reported N2 annealing methods. We find that IEMSOFET without a buried channel leads to a on-resistance (RDS(on)) of 50mΩ in case of a channel length of 0.5μm, compared to 75mΩ with buried channel. The simulations show that RDS(on) drops from 112mΩ to 75mΩ by annealing N2. For the device without buried channel, the corresponding decrease in RDS(on),with N2 anneal, is from 55mΩ to 50mΩ.

Keywords: Analog Circuits and Systems, Other Power Circuits and Systems
Abstract: Detecting nanosecond-scale voltage transients in GaN-HEMT gate-driver circuits requires comparators capable of resolving small input overdrive with minimal latency. This work presents a GaN-based comparator implemented using an enhancement-mode p-GaN cross-coupled latch architecture for transient detection in gate-driver protection applications. To address the trade-off between switching speed and effective trip-point stability associated with diode-connected load structures, a dynamic-assist technique is introduced in the output stage. The dynamic-assist GaN HEMT is activated only during switching, providing transient current enhancement without disturbing the DC operating point. Simulation results show that the proposed assist reduces the output rise time from 3.73 ns to 1.61 ns, corresponding to a 57% improvement, while achieving a propagation delay of 1.35 ns. The detector also maintains stable effective trip-point behavior and remains inactive under nominal 0–6V driver operation, confirming its suitability for high-speed transient detection in GaN gate-driver protection.

Keywords: Other Power Circuits and Systems
Abstract: Gate driver sizing in integrated converters critically affects both power stage loss and Miller induced false turn on. This motivates the segmented output stage design and sizing methodology presented in this paper. Analytical relations based on size set the high side pull down and low side pull up strengths, while fanout and width are optimized to limit delay and parasitic loading. Implemented in a 180 nm high voltage BCD process, the proposed sizing method identifies an operating region that reduces crosstalk risk and minimizes converter loss. The simulation and measurement results validate the effectiveness of the segmented last stage sizing approach and achieves a 94.07% efficiency in a hybrid DC-DC converter.

Keywords: Communications Systems and Control, Wireless Charging and Energy Harvesting, Other Wireless and Communications Topics
Abstract: This paper investigates a stealthy Trojan attack targeting the timer-based distributed retransmission mechanism of C-ARQ in energy-harvesting wireless networks. The attack subtly alters the timer of a compromised node, biasing retransmission selection and reducing its participation, which leads to energy imbalance, wasted energy, and degraded network performance. Experimental results show that at low energy harvesting rates, the attack can reduce the packet delivery ratio by up to 20%, demonstrating that even minor timer manipulations can significantly disrupt node selection. At higher energy harvesting rates, nodes maintain sufficient energy for retransmissions, reducing reliance on other nodes, including the compromised node, and thereby mitigating the attack’s effect and restoring network performance. These findings reveal a previously unexplored vulnerability in C-ARQ-based EH networks and underscore the need for robust, energy-aware mechanisms to ensure network reliability and resilience.

Keywords: RF Front-End Circuits, Mixed-Signal RF and Baseline Circuits, Analog Circuits and Systems
Abstract: Emerging AI/ML-driven wireless systems demand RF front-ends with dynamically reconfigurable performance rather than fixed operating points. To address this need, we present a reconfigurable double-balanced folded cascode CMOS active mixer designed in a 65nm CMOS process. Dual operating modes allow flexible trade-offs among conversion gain (CG), noise figure (NF), and linearity, while a digitally controlled current switching circuit (CSC) enables real-time parameter tuning via a 6-bit control word. Pre-layout simulations over 1–7GHz show a peak CG of 18.1 dB, an input-referred 1 dB compression point of 0 dBm, and a minimum NF of 9.5 dB. A Dueling Double Deep Q-Network (DQN) agent, trained on a differentiable digital twin of the mixer, validates AI-readiness by autonomously selecting optimal mode and switching current configurations across varying signal power and channel conditions in real time.

Keywords: Communications Circuits, Theory and Applications, RF Front-End Circuits, Other Analog/RF Circuits and Systems
Abstract: Modern wireless communication systems are typically analyzed using high-level analytical models that prioritize signal-to-noise ratios and bit-error rates, often at the expense of capturing the underlying circuit-level physics and hardware-specific non-idealities. This limits the ability to study the impact of physical parameters and hardware constraints on system performance. In this work, a SPICE-based emulator framework is developed for a physically consistent far-field (FF) single-input single-output (SISO) circuit model, enabling waveform-level analysis within a standard circuit simulation environment. The proposed framework translates a circuit-theoretic formulation into an HSPICE-compatible implementation, allowing direct observation of signal propagation, parameter sensitivity, and statistical variability. Sensitivity analysis is performed by varying key geometric parameters, including transmitter–receiver separation distance and antenna size, and evaluating their impact on peak, RMS, and mutual information (MI) metrics. A histogram-based approach is used to estimate MI from transient waveforms, providing an information-level perspective in addition to voltage-based metrics. Furthermore, a 10,000-point Monte Carlo simulation is conducted to assess the impact of simultaneous parameter variations and quantify system robustness. The results demonstrate that the proposed framework enables unified evaluation of deterministic behavior, information transfer, and variability, providing design-oriented insights for parameter selection in circuit-level implementations of far-field communication systems.

Keywords: Analog Circuits and Systems, Other Power Circuits and Systems, Communications Circuits, Theory and Applications
Abstract: We present a system that delivers galvanically isolated power and slow-control data through a single multimode optical fiber, targeting cryogenic detector readout applications. An 808 nm laser drives a multi-junction GaAs optical power converter (OPC) while Manchester-coded data is superimposed on the power carrier by modulating the laser drive current at ~0.4% fractional modulation depth. An AC-coupled receiver whose first stage is configured as a continuous-time linear equalizer (CTLE) recovers rail-to-rail logic from the resulting ~40 mVpp OPC voltage swing, extending the equalized channel bandwidth from 265 Hz to ~19 kHz. The complete system has been verified at room temperature and at 77 K (liquid nitrogen immersion) at data rates up to 2 kb/s, confirming its suitability for slow-control programming of cryogenic ASICs.

Keywords: Wireless Charging and Energy Harvesting, RF Front-End Circuits, Other Power Circuits and Systems
Abstract: outperforms the others throughout the evaluation power range (Pavl ∈ [−25,−10] dBm) at 2.45GHz. For all three DMNs, the system PCE exceeded 10% for Pavl ≥ −20dBm, with a peak PCE of approximately 40%.

This paper presents a novel automated design framework for the co-optimization of distributed matching network (DMN), diode-based rectifier and load parameters for ambient RF energy-harvesting systems. We report a framework that integrates the Keysight ADS command-line interface with the Python OOP functionality. By dynamically compiling a netlist from a library of elements, circuit configurations and modular Python classes to run Harmonic Balance and Large-Signal S-parameter simulations, the GUI dependency is eliminated. It maximizes the power conversion efficiency (PCE) for all user specified DMN and rectifier topologies and the range of available input power levels (Pavl). The proposed work reduces the design time to less than 45 min, which is a 25-fold improvement over the previous method, which is validated using three DMN topologies and a single-stage Dickson rectifier. The design is optimized for Pavl ∈ [−20,−15,−10]dBm, and the design at −20dBm outperforms the others throughout the evaluation power range (Pavl ∈ [−25,−10] dBm) at 2.45GHz. For all three DMNs, the system PCE exceeded 10% for Pavl ≥ −20dBm, with a peak PCE of approximately 40%.

Keywords: RF Front-End Circuits, Other Analog/RF Circuits and Systems, Analog Circuits and Systems
Abstract: Conventional CMOS rectifiers for radio-frequency (RF) energy harvesting exhibit a fundamental sensitivity– efficiency trade-off that limits their usable power dynamic range. This paper presents an adaptive dual-path rectifier in a 65-nm CMOS process that addresses this limitation by selecting between a low-power low-threshold voltage transistor (LVT) path and a high-power, high voltage threshold transistor (HVT) path based on the incoming RF power. A comparator-based control circuit monitors the rectifier output and switches between the two paths, isolating the inactive branch to suppress reverse leakage. Post layout extracted simulations at 900MHz and 2.4GHz show peak power conversion efficiencies (PCEs) of 60.1% and 59.0%, 1-V sensitivities of −37dBm and −33dBm measured at 5MΩ and 2MΩ loads, respectively, and power dynamic ranges of 35 dB and 32 dB characterized at 100 kΩ, with a post-layout active area of 0.057mm2.

Keywords: Wireless Charging and Energy Harvesting, Analog Circuits and Systems
Abstract: This paper presents vibration energy harvesting from a windmill using a piezoelectric cantilever (PZT) to power wireless sensors. The major design issue faced for the proposed power management circuit (PMC), specifically the oscillator and the voltage regulator, is cold start due to the low vibration energy level of windmills. The problem is addressed through a simple RC based network which only passes the valid oscillation signal and a transistor controlled RC network to delay the regulator start up, ensuring reliable cold start operation. The circuit is prototyped on a printed circuit board (PCB) with the size of 32 mm x 52 mm. The measurement results show that the PMC generates regulated DC of 3.7 V and delivered 518 uW under a vibration condition that produces an open circuit PZT output of 30 Hz, 30 V peak to peak which is used as a representative operating condition of the windmill to power a wireless sensor.

Keywords: Analog Circuits and Systems, System on a Chip (SOC) and Network on a Chip (NOC)
Abstract: An area and power efficient I/O voltage level converter (VLC) circuit is presented for off-chip communication. The 9-transistor topology, that is based on the current-mirror approach, has been demonstrated to scale well across multiple CMOS process nodes. Measurement results from 180nm and 65nm test chips, together with post-layout simulations at the 28nm node show the design to be robust in the presence of process, voltage, and temperature fluctuations. At the 180nm node, the proposed VLC occupies an area of 50.96µm2, consumes 630.9nW of switching power, and 102pW of leakage power.

Keywords: Technologies for Smart Sensors, Sensor Interface Circuits and Microsystems, Neuromorphic Circuits and Systems
Abstract: The design of camera pixels in low-geometry CMOS technology nodes is challenging due to limited voltage supply and resulting output swing. However, it is necessary for co-integration of sensor and machine learning on a chip. This paper revisit linear-logarithmic pixels, which can provide high dynamic range; however, suffer from high fixed pattern noise. It is argued that these pixels may be better suited for low technology nodes due to their requirement of only having a small output swing. Furthermore, machine learning classification tasks are shown to tolerate high FPN. A simple 3-parameter calibration strategy is then suggested to reduce the FPN in these pixels to levels required for these tasks, without significant computational complexity and validated with a pixel designed in 28nm CMOS process.

Keywords: Wearable Smart Sensor Systems, Internet of Things (IoT) Theory and Systems, Technologies for Smart Sensors
Abstract: Wearable health monitoring systems have gained significant attention due to their potential for continuous, non-invasive physiological data collection. Smart insoles offer a unique platform for capturing lower-body biomechanical and physiological signals without interfering with daily activities. This paper presents Heal Sole, a prototype smart insole system integrating heart rate, temperature, and blood oxygen saturation (SpO2) sensors with motor-assisted ankle rehabilitation and a web-based monitoring interface. The system employs an ESP32 microcontroller with low-cost commercial sensors (MAX30105, MLX90614), communicating via MQTT over TLS to a FastAPI backend with PostgreSQL storage and real-time WebSocket visualization. A dual-motor mechanism enables controlled dorsiflexion and plantarflexion exercises with automatic direction reversal at range-of-motion limits. Validation with five participants across 15 rehabilitation sessions generated 6,880 sensor readings transmitted without data loss, demonstrating reliable end-to-end system architecture. Sessions with valid sensor contact showed expected physiological responses, including a mean heart rate increase of 4.7 bpm following exercise.

Keywords: Wireless Mobile Circuits and Systems and Connectivity, Implantable/injectable Systems, Technologies for Smart Sensors
Abstract: Hydrocephalus is a disease caused by accumulation of cerebrospinal fluid (CSF) within the brain's ventricles, generally treated by implanting a drainage catheter (shunt valve). These shunts often fail due to clogging. Diagnosing shunt failure usually requires clinical imaging, which is inconvenient and often inconclusive. Integrating a flow sensor into the shunt system could improve care. Previous shunt flow sensor designs require active implanted electronics or bulky external readout systems. We successfully demonstrated proof-of-concept towards a simple wireless flow detection system based on harmonic generation. The implantable part of the system comprises an inductor coil and a pair of diodes, which emit third-order harmonics when interrogated by an AM signal from an external wearable coil. The implantable diode system can be combined with a passive flow-detecting switch to provide real-time binary flow detection.

Keywords: Implantable/injectable Systems, Integrated Biomedical Systems, Other Areas in Biomedical Circuits and Systems
Abstract: This research presents the post layout design and simulation of a wireless, fully integrated microchip that combines neural stimulation, neural recording, and fast-scan cyclic voltammetry-based dopamine sensing on a single platform. By integrating multimodal sensing, stimulation, and wireless telemetry circuits on a single ASIC, the proposed architecture provides a compact hardware platform for future closed-loop and adaptive neuromodulation systems, potentially enhancing monitoring and treatment efficacy for brain diseases. Designed in 65 nm CMOS, the system consumes 31.2 μW and occupies an active area of 340 μm × 320 μm, making it well-suited for distributed and minimally invasive neural implants.

Keywords: Sensor Interface Circuits and Microsystems, Implantable/injectable Systems, Human/brain-Machine Interfaces
Abstract: This paper investigates the challenges of acquiring reliable electrical and neural signals from organs such as the stomach, which presents a complex and highly dynamic environment for studying metabolic conditions like diabetes and obesity. A key requirement is maintaining a stable interface between electrodes and tissues in regions subject to continuous motion, mechanical forces, and vibrations. Various electrode array designs are reviewed with a focus on attachment strategies. To address these challenges, we propose a flexible, circular, ring-shaped electrode array that wraps circumferentially around the stomach to specifically target the region where vagal nerve branches connect near the upper portion of the rat stomach. This preliminary design aims to study further and characterize the challenges associated with implanting electrode arrays on or around motile organs. Physical attachment of the prototype electrode to a silicone model of the stomach shows that the design can maintain stability and remain flexible, while the effect of all types of forces will be fully characterized in our future work. At this stage, we have experimentally established the electrical functionality of the proposed electrode array by successfully capturing the generated neural signals in an agar-based in vitro test setup developed with an Intan RHD2132 multi-channel recording and stimulator circuit interface.

Keywords: Analog, Digital and Mixed Signal Processing, Communications Systems and Control
Abstract: A new aliased sinc (asinc) interpolation kernel for digital modulation is introduced. The asinc kernel provides a bandlimited and true low pass frequency response modulation waveform. The bandlimited asinc kernel results in a small, controlled amount of signal overshoot and inter-symbol interference. The new asinc symbol interpolation method reduces the bandwidth for 16 quadrature amplitude modulation (QAM) by ~24% compared to half cycle raised cosine QAM and greatly reduces the sidelobes.

Keywords: Signal Processing Theory and Methods, Other Signal and Image Processing, Digital Filters
Abstract: Continuous-time digital signal processing (CT-DSP) enables low-latency, event-driven processing by operating on asynchronous events rather than uniformly sampled data. Despite extensive research, its practical adoption has been limited by the lack of accessible, low-cost hardware, leading many studies to rely on simulation or specialized implementations. This paper presents a low-cost, open hardware add-on for the MicroNova Mercury 2 FPGA that converts analog inputs into asynchronous level-crossing events for CT-DSP. Built from off-the-shelf components, the daughterboard generates threshold based events without conventional sampling or anti-aliasing circuitry. Rather than proposing a new sampling principle, this work contributes an accessible, reproducible implementation of established level-crossing techniques, lowering the barrier to experimental CT-DSP. The board has been fabricated and tested, with circuit behavior validated in simulation. Schematics and reference designs are released open-source, with a commercial implementation supporting adoption in research and education.

Keywords: Neuromorphic Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Machine Learning at the Edge
Abstract: Spiking neural networks encode information in spike timing and offer a pathway toward energy efficient artificial intelligence. However, a key challenge in spiking neural networks is realizing nonlinear and expressive computation in compact, energy-efficient hardware without relying on additional circuit complexity. In this work, we examine nonlinear computation in a CMOS+X spiking neuron implemented with a magnetic tunnel junction connected in series with an NMOS transistor. Circuit simulations of a multilayer network solving the XOR classification problem show that three intrinsic neuronal properties enable nonlinear behavior: threshold activation, response latency, and absolute refraction. Threshold activation determines which neurons participate in computation, response latency shifts spike timing, and absolute refraction suppresses subsequent spikes. These results show that MTJ magnetization dynamics can support timing-based nonlinear computation in the NMOS+MTJ architecture studied here.

Keywords: Emerging Memory and Memristor, Neuromorphic Circuits and Systems, Neuromorphic System Algorithms and Applications
Abstract: Neuromorphic computing has made significant strides over the past few years by mapping functional primitives of neurons and synapses to nanoelectronic devices, yet most implementations do not tap into the temporal non-linear dynamics of the devices. We argue that spintronic devices, specifically magnetic tunnel junctions (MTJs), offer a palette of intrinsic physical phenomena that can serve as native computational primitives. Spin-transfer torque (STT), spin-orbit torque (SOT), voltage-controlled magnetic anisotropy (VCMA), magnetoelectric effect (ME) and stochastic superparamagnetic dynamics each enable functionalities difficult to replicate in deterministic CMOS. We underscore this perspective through two specific system-level instances focusing on the synapse and neuron: selectorless synaptic crossbar arrays that exploit a VCMA-driven switching-mechanism to eliminate per-cell selectors, and temporal information encoding through superparamagnetic neuronal MTJs that achieves significant network-level spiking sparsity via stochastic dynamics. Building on these exemplars, we envision how these primitives compose with the broader spintronic ecosystem --- domain-wall synapses, oscillatory primitives, and stochastic neurons --- toward neuromorphic systems that are simultaneously sparser, denser, and more functionally diverse.

Keywords: Emerging Memory and Memristor, Neural Learning System Algorithms and Applications, Machine Learning at the Edge
Abstract: Spiking neural networks (SNNs) are well suited for low-power inference, particularly when implemented in analog hardware. However, in analog SNNs, synaptic elements dominate area and strongly influence scalability and robustness, making efficient synapse design a key challenge. Non-volatile devices are therefore attractive for synaptic weight storage, and molecular field-effect transistors (FETs) offer compact, persistent switching behavior suitable for analog integration. This work proposes a novel programmable synapse architecture constructed from binary molecular FET devices, where multi-bit weights are realized architecturally using power-of-two-scaled gate geometries. A hardware-aware training and mapping framework is developed and validated using SPICE-level circuit simulations alongside system-level PyTorch models of the proposed synapse. We further analyze the robustness of the proposed architecture to synaptic non-idealities arising from finite on-off ratio. These results indicate that architecturally constructed programmable synapses from simple binary molecular devices provide a robust and scalable approach for analog SNN hardware.

Keywords: In-Memory Computing Circuits and Systems, AI Analog and Mixed-Signal Architectures, Accelerators, and Circuits, Emerging Memory and Memristor
Abstract: ReRAM-based in-memory computing (IMC) architectures are promising candidates for energy-efficient matrix-vector multiplication. While scaling the size of ReRAM arrays allows for the amortization of power-hungry peripheral circuits like DACs and ADCs, it simultaneously introduces more parasitic along the signal path. Because of these challenges, current design methodologies often lack practical guidelines to balance these effects at early design stage, forcing designers to rely on time-consuming, iterative transistor-level simulations.

In this work, we propose a comprehensive framework for design space exploration that enables the selection of optimal array size, ADC resolution, and system frequency without requiring exhaustive simulations. The framework utilizes a specialized testbench to extract parameters from a limited set of representative transistor-level simulations. These parameters are then used to accurately predict the performance of arbitrary architectures. We demonstrate the effectiveness of this framework through two realistic design cases aimed at maximizing energy efficiency (TOPs/s/W). The results show that the framework successfully identifies optimal architectural configurations under strict power and error constraints, providing an efficient path for high-performance IMC design.

Keywords: Secure AI Hardware, Heterogeneous Integration, Hardware Security
Abstract: The rise of chiplet-based AI accelerators creates a critical security gap: untrusted, black-box components can introduce malicious backdoors, yet their nature renders traditional software defenses impractical. To close this gap, we propose TrustNoC, the first trustworthy interposer architecture that embeds a novel backdoor filter ensemble (BFE) into its network-on-chip routers to filter malicious data in-transit without modifying the AI models or the chiplets themselves. Our evaluation shows TrustNoC effectively suppresses backdoor attacks, reducing the attack success rate to 0.5% while maintaining model accuracy above 90%. This robust hardware-level security is achieved with a low footprint, requiring <10% of the total interposer area to maintain high yield. Thus, TrustNoC establishes the silicon interposer as a new hardware defense layer, offering a practical solution for secure AI inference in heterogeneous chiplet systems.

Keywords: Hardware Security, Heterogeneous Integration, System on a Chip (SOC) and Network on a Chip (NOC)
Abstract: Modern computing systems are transitioning from large-scale monolithic SoCs toward modular heterogeneous chiplet systems. The smaller chiplets are integrated on a substrate/interposer and connected using a Network-on-Package. Chiplet-based integration brings several new advantages such as performance improvement and cost reduction through yield benefits, heterogeneity, and reuse. Despite these advantages, heterogeneity also brings new security challenges. As more mutually untrusted chiplets are integrated into a shared substrate, complex cross-component attacks (e.g., a covert channel between CPU/GPU) are rising.

The main insight of this paper is that the Network-on-Package (NoP) offers a unique opportunity to develop a comprehensive and cost-effective monitoring framework to address increasing security concerns in heterogeneous systems. This new component can specifically monitor the communication packets exchanged among various chiplets, such as the CPU, GPU, and memory, to detect different attacks. Specifically, by integrating this security feature, the system can protect against unauthorized or malicious communication between components, helping to reduce the risk of emerging cross-component attacks, such as covert channels. Our main contribution is to design and implement this security component called the HEterogeneous secuRity Analyzer (HERA). We carefully design various aspects of our system to balance security and overhead.

Keywords: System on a Chip (SOC) and Network on a Chip (NOC), Hardware Security
Abstract: Chiplet-based hybrid interconnection networks that incorporate wired and wireless communications provide high performance and energy efficiency; however, the wireless reservation logic in these networks is exposed to vulnerabilities in the control plane. This study describes a control-state deception attack on a chiplet-based hybrid interconnection network, in which a malicious router or network interface generates a fake control-state for a reservation, indicating the wireless interface's apparent inability to support communication, thereby routing legitimate inter-chiplet communication traffic through the wired/interposer link. In contrast to other existing jamming-based attacks, this particular threat can be executed without relying on a high packet injection rate. In order to protect hybrid interconnects from such attacks, we propose a machine learning-based security framework based on the use of random forest, XGBoost and Artificial Neural Network (ANN) models. The experimental results show that the proposed ANN-based framework achieves the highest control-state deception detection accuracy of 88.34%, a 18% speedup, and a 45% reduction in network latency compared to the attacked system without defense. These results highlight the importance of protecting the wireless control plane in future chiplet-based hybrid interconnection systems.

Keywords: Heterogeneous Integration, Hardware Security, Processor and Memory Design and Architectures
Abstract: The semiconductor industry is rapidly transitioning from monolithic systems-on-chip toward heterogeneous, multi- vendor 2.5D chiplet ecosystems integrated via silicon interposers. While this paradigm shift offers immense benefits in yield, cost, and time-to-market, it radically expands the attack surface. Integrating chiplets from untrusted foundries and design houses introduces vulnerabilities to hardware Trojans, IP piracy, and system-level communication exploits. Critically, chip-level secu- rity features and conventional Root of Trust (RoT) proposals are insufficient in this context: any component, including the interconnect fabric itself, may be sourced from an untrusted vendor. This review surveys state-of-the-art security strategies for interposer-based 2.5D integration, focusing on three threat categories: interconnect attacks (snooping, spoofing, and man-in- the-middle), cache coherence exploits including complex forging attacks, and microarchitectural side-channel threats. We examine design-time defenses via 2.5D split manufacturing and, more crucially, runtime defenses that establish an active interposer as a physically isolated 2.5D RoT. By embedding so-called transaction monitors and coherence message checkers within the trusted interposer fabric, the system enforces memory access permissions by construction and neutralizes coherence-level attacks without need for modifying/securing the commodity chiplets. Finally, we review the EDA flows required to realize these defenses and show they concurrently improve power and signal integrity while reducing overall system footprint.

Keywords: AI-IoT Systems and Applications, RF Front-End Circuits, Machine Learning at the Edge
Abstract: Low-power systems such as Internet of Things (IoT) devices, wireless sensor networks, wearables, and biomedical devices increasingly need power sources beyond conventional batteries. Because batteries have limited lifetimes and environmental costs, RF energy harvesting is an attractive alternative for self-sustaining operation. This work presents a machine-learning circuit-optimization model for RF energy harvesters, with a focus on rectifier design. The model is implemented as a surrogate-assisted sweep-wise operating-point selection framework. The rectifier is treated as a black-box system, and two surrogate candidates-a machine-learning hybrid and a shape-preserving interpolant-are fitted and compared using datasets from a three-stage rectifier in TSMC 65-nm. By assigning user-defined weights to performance metrics such as power conversion efficiency (PCE) and output voltage (VOUT), the model enables preference-weighted sweep-wise operating-point selection. Given desired output targets, the model identifies preferred sweep values of input power (Pin), load resistance (RL), or frequency. Each selection is made on a one-dimensional sweep with the remaining variables held fixed. The framework therefore performs a conditional inverse lookup over the sampled operating space. After the initial SPICE sweep dataset is generated, the framework reduces repeated manual sweep inspection and supports rapid operating-point exploration. Additional off-grid SPICE checks show average absolute differences of 0.84% in PCE and 44.8 mV in VOUT.

Keywords: Neuromorphic Circuits and Systems, Neuromorphic System Algorithms and Applications, Analog Circuits and Systems
Abstract: We present a compact, programmable CMOS Izhikevich neuron in 65 nm CMOS technology that reproduces biologically diverse firing regimes within a single configurablecell. Two key innovations address limitations of prior analog realizations: a fixed-width spike pulse that decouples reset dynamics from threshold overdrive, and a switched-capacitor adaptation circuit that implements the recovery increment as a precise capacitor-ratio quantity, eliminating pulse-width-dependent variability. Circuit parameters are mapped from the analytical model via nullcline analysis, and voltage and time scaling, with the MOSFET subthreshold characteristic approximating the quadratic membrane nonlinearity near the saddle-node bifurcation. Cadence Spectre simulations confirm regular spiking, fast spiking, and chattering modes at 418 nW static power and 5 fJ/spike, competitive with state-of-the-art neuromorphic designs.

Keywords: Digital Integrated Circuits, AI Digital Hardware, Accelerators, and Circuits, AI-IoT Systems and Applications
Abstract: This paper introduces MAI-EDA, a multi-agent AI co-pilot framework for personalized EDA education in which the RTL-to-GDSII flow is decomposed into modular tasks coordinated by Specialist Agents. Each Specialist Agent invokes a stage-specific open-source EDA tool (Yosys, OpenROAD, OpenSTA, or Verilator) on the SkyWater SKY130 PDK. A learner-profile-aware Orchestrator Agent routes queries between Specialist Agents, exposing cross-stage reasoning to learners when a problem's root cause lies in an earlier stage of the flow. MAI-EDA provides context-aware assistance for design exploration, constraint management, debugging, and optimization, adapting to learner progress through natural language interaction. The curriculum is organized as chapters mapped one-to-one to Specialist Agents, with each chapter divided into Basic, Intermediate, and Advanced levels. We evaluate MAI-EDA on 40 tool-execution tasks and 20 routing queries, achieving 82.5% tool-invocation success, 90.0% output-parsing accuracy, and 100.0% routing correctness. Three case studies further illustrate guided debugging, multi-stage optimization, and profile-driven adaptation. Future work includes adding Specialist Agents for additional design domains and conducting cohort studies, with the goal of scaling personalized training for the next generation of semiconductor designers.